1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASM_ARCH_MX6SL_DDR_H__ 8*4882a593Smuzhiyun #define __ASM_ARCH_MX6SL_DDR_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef CONFIG_MX6SL 11*4882a593Smuzhiyun #error "wrong CPU" 12*4882a593Smuzhiyun #endif 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MX6_IOM_DRAM_CAS_B 0x020e0300 15*4882a593Smuzhiyun #define MX6_IOM_DRAM_CS0_B 0x020e0304 16*4882a593Smuzhiyun #define MX6_IOM_DRAM_CS1_B 0x020e0308 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM0 0x020e030c 19*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM1 0x020e0310 20*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM2 0x020e0314 21*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM3 0x020e0318 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MX6_IOM_DRAM_RAS_B 0x020e031c 24*4882a593Smuzhiyun #define MX6_IOM_DRAM_RESET 0x020e0320 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDBA0 0x020e0324 27*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDBA1 0x020e0328 28*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDBA2 0x020e032c 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCKE0 0x020e0330 31*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCKE1 0x020e0334 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCLK0_P 0x020e0338 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define MX6_IOM_DRAM_ODT0 0x020e033c 36*4882a593Smuzhiyun #define MX6_IOM_DRAM_ODT1 0x020e0340 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS0_P 0x020e0344 39*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS1_P 0x020e0348 40*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS2_P 0x020e034c 41*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS3_P 0x020e0350 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDWE_B 0x020e0354 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif /*__ASM_ARCH_MX6SL_DDR_H__ */ 46