1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013 Boundary Devices Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __ASM_ARCH_MX6Q_DDR_H__ 7*4882a593Smuzhiyun #define __ASM_ARCH_MX6Q_DDR_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef CONFIG_MX6Q 10*4882a593Smuzhiyun #error "wrong CPU" 11*4882a593Smuzhiyun #endif 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM0 0x020e05ac 14*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM1 0x020e05b4 15*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM2 0x020e0528 16*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM3 0x020e0520 17*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM4 0x020e0514 18*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM5 0x020e0510 19*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM6 0x020e05bc 20*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM7 0x020e05c4 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define MX6_IOM_DRAM_CAS 0x020e056c 23*4882a593Smuzhiyun #define MX6_IOM_DRAM_RAS 0x020e0578 24*4882a593Smuzhiyun #define MX6_IOM_DRAM_RESET 0x020e057c 25*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCLK_0 0x020e0588 26*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCLK_1 0x020e0594 27*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDBA2 0x020e058c 28*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCKE0 0x020e0590 29*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCKE1 0x020e0598 30*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDODT0 0x020e059c 31*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDODT1 0x020e05a0 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS0 0x020e05a8 34*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS1 0x020e05b0 35*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS2 0x020e0524 36*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS3 0x020e051c 37*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS4 0x020e0518 38*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS5 0x020e050c 39*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS6 0x020e05b8 40*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS7 0x020e05c0 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define MX6_IOM_GRP_B0DS 0x020e0784 43*4882a593Smuzhiyun #define MX6_IOM_GRP_B1DS 0x020e0788 44*4882a593Smuzhiyun #define MX6_IOM_GRP_B2DS 0x020e0794 45*4882a593Smuzhiyun #define MX6_IOM_GRP_B3DS 0x020e079c 46*4882a593Smuzhiyun #define MX6_IOM_GRP_B4DS 0x020e07a0 47*4882a593Smuzhiyun #define MX6_IOM_GRP_B5DS 0x020e07a4 48*4882a593Smuzhiyun #define MX6_IOM_GRP_B6DS 0x020e07a8 49*4882a593Smuzhiyun #define MX6_IOM_GRP_B7DS 0x020e0748 50*4882a593Smuzhiyun #define MX6_IOM_GRP_ADDDS 0x020e074c 51*4882a593Smuzhiyun #define MX6_IOM_DDRMODE_CTL 0x020e0750 52*4882a593Smuzhiyun #define MX6_IOM_GRP_DDRPKE 0x020e0758 53*4882a593Smuzhiyun #define MX6_IOM_GRP_DDRMODE 0x020e0774 54*4882a593Smuzhiyun #define MX6_IOM_GRP_CTLDS 0x020e078c 55*4882a593Smuzhiyun #define MX6_IOM_GRP_DDR_TYPE 0x020e0798 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif /*__ASM_ARCH_MX6Q_DDR_H__ */ 58