1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013 Boundary Devices Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __ASM_ARCH_MX6DLS_DDR_H__ 7*4882a593Smuzhiyun #define __ASM_ARCH_MX6DLS_DDR_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef CONFIG_MX6DL 10*4882a593Smuzhiyun #ifndef CONFIG_MX6S 11*4882a593Smuzhiyun #error "wrong CPU" 12*4882a593Smuzhiyun #endif 13*4882a593Smuzhiyun #endif 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM0 0x020e0470 16*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM1 0x020e0474 17*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM2 0x020e0478 18*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM3 0x020e047c 19*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM4 0x020e0480 20*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM5 0x020e0484 21*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM6 0x020e0488 22*4882a593Smuzhiyun #define MX6_IOM_DRAM_DQM7 0x020e048c 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define MX6_IOM_DRAM_CAS 0x020e0464 25*4882a593Smuzhiyun #define MX6_IOM_DRAM_RAS 0x020e0490 26*4882a593Smuzhiyun #define MX6_IOM_DRAM_RESET 0x020e0494 27*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCLK_0 0x020e04ac 28*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCLK_1 0x020e04b0 29*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDBA2 0x020e04a0 30*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCKE0 0x020e04a4 31*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDCKE1 0x020e04a8 32*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDODT0 0x020e04b4 33*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDODT1 0x020e04b8 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS0 0x020e04bc 36*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS1 0x020e04c0 37*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS2 0x020e04c4 38*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS3 0x020e04c8 39*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS4 0x020e04cc 40*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS5 0x020e04d0 41*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS6 0x020e04d4 42*4882a593Smuzhiyun #define MX6_IOM_DRAM_SDQS7 0x020e04d8 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define MX6_IOM_GRP_B0DS 0x020e0764 45*4882a593Smuzhiyun #define MX6_IOM_GRP_B1DS 0x020e0770 46*4882a593Smuzhiyun #define MX6_IOM_GRP_B2DS 0x020e0778 47*4882a593Smuzhiyun #define MX6_IOM_GRP_B3DS 0x020e077c 48*4882a593Smuzhiyun #define MX6_IOM_GRP_B4DS 0x020e0780 49*4882a593Smuzhiyun #define MX6_IOM_GRP_B5DS 0x020e0784 50*4882a593Smuzhiyun #define MX6_IOM_GRP_B6DS 0x020e078c 51*4882a593Smuzhiyun #define MX6_IOM_GRP_B7DS 0x020e0748 52*4882a593Smuzhiyun #define MX6_IOM_GRP_ADDDS 0x020e074c 53*4882a593Smuzhiyun #define MX6_IOM_DDRMODE_CTL 0x020e0750 54*4882a593Smuzhiyun #define MX6_IOM_GRP_DDRPKE 0x020e0754 55*4882a593Smuzhiyun #define MX6_IOM_GRP_DDRMODE 0x020e0760 56*4882a593Smuzhiyun #define MX6_IOM_GRP_CTLDS 0x020e076c 57*4882a593Smuzhiyun #define MX6_IOM_GRP_DDR_TYPE 0x020e0774 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif /*__ASM_ARCH_MX6S_DDR_H__ */ 60