1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARCH_CLOCK_H 9*4882a593Smuzhiyun #define __ASM_ARCH_CLOCK_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef CONFIG_SYS_MX6_HCLK 14*4882a593Smuzhiyun #define MXC_HCLK CONFIG_SYS_MX6_HCLK 15*4882a593Smuzhiyun #else 16*4882a593Smuzhiyun #define MXC_HCLK 24000000 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifdef CONFIG_SYS_MX6_CLK32 20*4882a593Smuzhiyun #define MXC_CLK32 CONFIG_SYS_MX6_CLK32 21*4882a593Smuzhiyun #else 22*4882a593Smuzhiyun #define MXC_CLK32 32768 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enum mxc_clock { 26*4882a593Smuzhiyun MXC_ARM_CLK = 0, 27*4882a593Smuzhiyun MXC_PER_CLK, 28*4882a593Smuzhiyun MXC_AHB_CLK, 29*4882a593Smuzhiyun MXC_IPG_CLK, 30*4882a593Smuzhiyun MXC_IPG_PERCLK, 31*4882a593Smuzhiyun MXC_UART_CLK, 32*4882a593Smuzhiyun MXC_CSPI_CLK, 33*4882a593Smuzhiyun MXC_AXI_CLK, 34*4882a593Smuzhiyun MXC_EMI_SLOW_CLK, 35*4882a593Smuzhiyun MXC_DDR_CLK, 36*4882a593Smuzhiyun MXC_ESDHC_CLK, 37*4882a593Smuzhiyun MXC_ESDHC2_CLK, 38*4882a593Smuzhiyun MXC_ESDHC3_CLK, 39*4882a593Smuzhiyun MXC_ESDHC4_CLK, 40*4882a593Smuzhiyun MXC_SATA_CLK, 41*4882a593Smuzhiyun MXC_NFC_CLK, 42*4882a593Smuzhiyun MXC_I2C_CLK, 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun enum ldb_di_clock { 46*4882a593Smuzhiyun MXC_PLL5_CLK = 0, 47*4882a593Smuzhiyun MXC_PLL2_PFD0_CLK, 48*4882a593Smuzhiyun MXC_PLL2_PFD2_CLK, 49*4882a593Smuzhiyun MXC_MMDC_CH1_CLK, 50*4882a593Smuzhiyun MXC_PLL3_SW_CLK, 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun enum enet_freq { 54*4882a593Smuzhiyun ENET_25MHZ, 55*4882a593Smuzhiyun ENET_50MHZ, 56*4882a593Smuzhiyun ENET_100MHZ, 57*4882a593Smuzhiyun ENET_125MHZ, 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun u32 imx_get_uartclk(void); 61*4882a593Smuzhiyun u32 imx_get_fecclk(void); 62*4882a593Smuzhiyun unsigned int mxc_get_clock(enum mxc_clock clk); 63*4882a593Smuzhiyun void setup_gpmi_io_clk(u32 cfg); 64*4882a593Smuzhiyun void hab_caam_clock_enable(unsigned char enable); 65*4882a593Smuzhiyun void enable_ocotp_clk(unsigned char enable); 66*4882a593Smuzhiyun void enable_usboh3_clk(unsigned char enable); 67*4882a593Smuzhiyun void enable_uart_clk(unsigned char enable); 68*4882a593Smuzhiyun int enable_usdhc_clk(unsigned char enable, unsigned bus_num); 69*4882a593Smuzhiyun int enable_sata_clock(void); 70*4882a593Smuzhiyun void disable_sata_clock(void); 71*4882a593Smuzhiyun int enable_pcie_clock(void); 72*4882a593Smuzhiyun int enable_i2c_clk(unsigned char enable, unsigned i2c_num); 73*4882a593Smuzhiyun int enable_spi_clk(unsigned char enable, unsigned spi_num); 74*4882a593Smuzhiyun void enable_ipu_clock(void); 75*4882a593Smuzhiyun int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); 76*4882a593Smuzhiyun void enable_enet_clk(unsigned char enable); 77*4882a593Smuzhiyun int enable_lcdif_clock(u32 base_addr, bool enable); 78*4882a593Smuzhiyun void enable_qspi_clk(int qspi_num); 79*4882a593Smuzhiyun void enable_thermal_clk(void); 80*4882a593Smuzhiyun void mxs_set_lcdclk(u32 base_addr, u32 freq); 81*4882a593Smuzhiyun void select_ldb_di_clock_source(enum ldb_di_clock clk); 82*4882a593Smuzhiyun void enable_eim_clk(unsigned char enable); 83*4882a593Smuzhiyun #endif /* __ASM_ARCH_CLOCK_H */ 84