1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <asm/arch/imx-regs.h> 10*4882a593Smuzhiyun#include <generated/asm-offsets.h> 11*4882a593Smuzhiyun#include <asm/macro.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/* 14*4882a593Smuzhiyun * AIPS setup - Only setup MPROTx registers. 15*4882a593Smuzhiyun * The PACR default values are good. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * Default argument values: 18*4882a593Smuzhiyun * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to 19*4882a593Smuzhiyun * user-mode. 20*4882a593Smuzhiyun * - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for 21*4882a593Smuzhiyun * SDMA to access them. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun.macro init_aips mpr=0x77777777, opacr=0x00000000 24*4882a593Smuzhiyun ldr r0, =AIPS1_BASE_ADDR 25*4882a593Smuzhiyun ldr r1, =\mpr 26*4882a593Smuzhiyun str r1, [r0, #AIPS_MPR_0_7] 27*4882a593Smuzhiyun str r1, [r0, #AIPS_MPR_8_15] 28*4882a593Smuzhiyun ldr r2, =AIPS2_BASE_ADDR 29*4882a593Smuzhiyun str r1, [r2, #AIPS_MPR_0_7] 30*4882a593Smuzhiyun str r1, [r2, #AIPS_MPR_8_15] 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Did not change the AIPS control registers access type. */ 33*4882a593Smuzhiyun ldr r1, =\opacr 34*4882a593Smuzhiyun str r1, [r0, #AIPS_OPACR_0_7] 35*4882a593Smuzhiyun str r1, [r0, #AIPS_OPACR_8_15] 36*4882a593Smuzhiyun str r1, [r0, #AIPS_OPACR_16_23] 37*4882a593Smuzhiyun str r1, [r0, #AIPS_OPACR_24_31] 38*4882a593Smuzhiyun str r1, [r0, #AIPS_OPACR_32_39] 39*4882a593Smuzhiyun str r1, [r2, #AIPS_OPACR_0_7] 40*4882a593Smuzhiyun str r1, [r2, #AIPS_OPACR_8_15] 41*4882a593Smuzhiyun str r1, [r2, #AIPS_OPACR_16_23] 42*4882a593Smuzhiyun str r1, [r2, #AIPS_OPACR_24_31] 43*4882a593Smuzhiyun str r1, [r2, #AIPS_OPACR_32_39] 44*4882a593Smuzhiyun.endm 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun/* 47*4882a593Smuzhiyun * MAX (Multi-Layer AHB Crossbar Switch) setup 48*4882a593Smuzhiyun * 49*4882a593Smuzhiyun * Default argument values: 50*4882a593Smuzhiyun * - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1 51*4882a593Smuzhiyun * - SGPCR: always park on last master 52*4882a593Smuzhiyun * - MGPCR: restore default values 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000 55*4882a593Smuzhiyun ldr r0, =MAX_BASE_ADDR 56*4882a593Smuzhiyun ldr r1, =\mpr 57*4882a593Smuzhiyun str r1, [r0, #MAX_MPR0] /* for S0 */ 58*4882a593Smuzhiyun str r1, [r0, #MAX_MPR1] /* for S1 */ 59*4882a593Smuzhiyun str r1, [r0, #MAX_MPR2] /* for S2 */ 60*4882a593Smuzhiyun str r1, [r0, #MAX_MPR3] /* for S3 */ 61*4882a593Smuzhiyun str r1, [r0, #MAX_MPR4] /* for S4 */ 62*4882a593Smuzhiyun ldr r1, =\sgpcr 63*4882a593Smuzhiyun str r1, [r0, #MAX_SGPCR0] /* for S0 */ 64*4882a593Smuzhiyun str r1, [r0, #MAX_SGPCR1] /* for S1 */ 65*4882a593Smuzhiyun str r1, [r0, #MAX_SGPCR2] /* for S2 */ 66*4882a593Smuzhiyun str r1, [r0, #MAX_SGPCR3] /* for S3 */ 67*4882a593Smuzhiyun str r1, [r0, #MAX_SGPCR4] /* for S4 */ 68*4882a593Smuzhiyun ldr r1, =\mgpcr 69*4882a593Smuzhiyun str r1, [r0, #MAX_MGPCR0] /* for M0 */ 70*4882a593Smuzhiyun str r1, [r0, #MAX_MGPCR1] /* for M1 */ 71*4882a593Smuzhiyun str r1, [r0, #MAX_MGPCR2] /* for M2 */ 72*4882a593Smuzhiyun str r1, [r0, #MAX_MGPCR3] /* for M3 */ 73*4882a593Smuzhiyun str r1, [r0, #MAX_MGPCR4] /* for M4 */ 74*4882a593Smuzhiyun str r1, [r0, #MAX_MGPCR5] /* for M5 */ 75*4882a593Smuzhiyun.endm 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun/* 78*4882a593Smuzhiyun * M3IF setup 79*4882a593Smuzhiyun * 80*4882a593Smuzhiyun * Default argument values: 81*4882a593Smuzhiyun * - CTL: 82*4882a593Smuzhiyun * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 83*4882a593Smuzhiyun * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000 84*4882a593Smuzhiyun * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000 85*4882a593Smuzhiyun * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 86*4882a593Smuzhiyun * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 87*4882a593Smuzhiyun * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 88*4882a593Smuzhiyun * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 89*4882a593Smuzhiyun * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 90*4882a593Smuzhiyun * ------------ 91*4882a593Smuzhiyun * 0x00000040 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun.macro init_m3if ctl=0x00000040 94*4882a593Smuzhiyun /* M3IF Control Register (M3IFCTL) */ 95*4882a593Smuzhiyun write32 M3IF_BASE_ADDR, \ctl 96*4882a593Smuzhiyun.endm 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun.macro core_init 99*4882a593Smuzhiyun mrc p15, 0, r1, c1, c0, 0 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* Set branch prediction enable */ 102*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 1 103*4882a593Smuzhiyun orr r0, r0, #7 104*4882a593Smuzhiyun mcr p15, 0, r0, c1, c0, 1 105*4882a593Smuzhiyun orr r1, r1, #1 << 11 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* Set unaligned access enable */ 108*4882a593Smuzhiyun orr r1, r1, #1 << 22 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Set low int latency enable */ 111*4882a593Smuzhiyun orr r1, r1, #1 << 21 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun mcr p15, 0, r1, c1, c0, 0 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun mov r0, #0 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun mcr p15, 0, r0, c15, c2, 4 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */ 120*4882a593Smuzhiyun mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */ 121*4882a593Smuzhiyun mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* Setup the Peripheral Port Memory Remap Register */ 124*4882a593Smuzhiyun ldr r0, =0x40000015 /* Start from AIPS 2-GB region */ 125*4882a593Smuzhiyun mcr p15, 0, r0, c15, c2, 4 126*4882a593Smuzhiyun.endm 127