1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARCH_CLOCK_H 9*4882a593Smuzhiyun #define __ASM_ARCH_CLOCK_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef CONFIG_MX35_HCLK_FREQ 14*4882a593Smuzhiyun #define MXC_HCLK CONFIG_MX35_HCLK_FREQ 15*4882a593Smuzhiyun #else 16*4882a593Smuzhiyun #define MXC_HCLK 24000000 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifdef CONFIG_MX35_CLK32 20*4882a593Smuzhiyun #define MXC_CLK32 CONFIG_MX35_CLK32 21*4882a593Smuzhiyun #else 22*4882a593Smuzhiyun #define MXC_CLK32 32768 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enum mxc_clock { 26*4882a593Smuzhiyun MXC_ARM_CLK, 27*4882a593Smuzhiyun MXC_AHB_CLK, 28*4882a593Smuzhiyun MXC_IPG_CLK, 29*4882a593Smuzhiyun MXC_IPG_PERCLK, 30*4882a593Smuzhiyun MXC_UART_CLK, 31*4882a593Smuzhiyun MXC_ESDHC1_CLK, 32*4882a593Smuzhiyun MXC_ESDHC2_CLK, 33*4882a593Smuzhiyun MXC_ESDHC3_CLK, 34*4882a593Smuzhiyun MXC_USB_CLK, 35*4882a593Smuzhiyun MXC_CSPI_CLK, 36*4882a593Smuzhiyun MXC_FEC_CLK, 37*4882a593Smuzhiyun MXC_I2C_CLK, 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun enum mxc_main_clock { 41*4882a593Smuzhiyun CPU_CLK, 42*4882a593Smuzhiyun AHB_CLK, 43*4882a593Smuzhiyun IPG_CLK, 44*4882a593Smuzhiyun IPG_PER_CLK, 45*4882a593Smuzhiyun NFC_CLK, 46*4882a593Smuzhiyun USB_CLK, 47*4882a593Smuzhiyun HSP_CLK, 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun enum mxc_peri_clock { 51*4882a593Smuzhiyun UART1_BAUD, 52*4882a593Smuzhiyun UART2_BAUD, 53*4882a593Smuzhiyun UART3_BAUD, 54*4882a593Smuzhiyun SSI1_BAUD, 55*4882a593Smuzhiyun SSI2_BAUD, 56*4882a593Smuzhiyun CSI_BAUD, 57*4882a593Smuzhiyun MSHC_CLK, 58*4882a593Smuzhiyun ESDHC1_CLK, 59*4882a593Smuzhiyun ESDHC2_CLK, 60*4882a593Smuzhiyun ESDHC3_CLK, 61*4882a593Smuzhiyun SPDIF_CLK, 62*4882a593Smuzhiyun SPI1_CLK, 63*4882a593Smuzhiyun SPI2_CLK, 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun u32 imx_get_uartclk(void); 67*4882a593Smuzhiyun u32 imx_get_fecclk(void); 68*4882a593Smuzhiyun unsigned int mxc_get_clock(enum mxc_clock clk); 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* __ASM_ARCH_CLOCK_H */ 71