1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARCH_CLOCK_H 9*4882a593Smuzhiyun #define __ASM_ARCH_CLOCK_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef CONFIG_MX31_HCLK_FREQ 14*4882a593Smuzhiyun #define MXC_HCLK CONFIG_MX31_HCLK_FREQ 15*4882a593Smuzhiyun #else 16*4882a593Smuzhiyun #define MXC_HCLK 26000000 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifdef CONFIG_MX31_CLK32 20*4882a593Smuzhiyun #define MXC_CLK32 CONFIG_MX31_CLK32 21*4882a593Smuzhiyun #else 22*4882a593Smuzhiyun #define MXC_CLK32 32768 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enum mxc_clock { 26*4882a593Smuzhiyun MXC_ARM_CLK, 27*4882a593Smuzhiyun MXC_IPG_CLK, 28*4882a593Smuzhiyun MXC_IPG_PERCLK, 29*4882a593Smuzhiyun MXC_CSPI_CLK, 30*4882a593Smuzhiyun MXC_UART_CLK, 31*4882a593Smuzhiyun MXC_IPU_CLK, 32*4882a593Smuzhiyun MXC_ESDHC_CLK, 33*4882a593Smuzhiyun MXC_I2C_CLK, 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun unsigned int mxc_get_clock(enum mxc_clock clk); 37*4882a593Smuzhiyun extern u32 imx_get_uartclk(void); 38*4882a593Smuzhiyun extern void mx31_gpio_mux(unsigned long mode); 39*4882a593Smuzhiyun extern void mx31_set_pad(enum iomux_pins pin, u32 config); 40*4882a593Smuzhiyun extern void mx31_set_gpr(enum iomux_gp_func gp, char en); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun void mx31_uart1_hw_init(void); 43*4882a593Smuzhiyun void mx31_uart2_hw_init(void); 44*4882a593Smuzhiyun void mx31_spi2_hw_init(void); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif /* __ASM_ARCH_CLOCK_H */ 47