1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * Matthias Weisser <weisserm@arcor.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2009 DENX Software Engineering 6*4882a593Smuzhiyun * Author: John Rigby <jrigby@gmail.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Common asm macros for imx25 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __ASM_ARM_ARCH_MACRO_H__ 14*4882a593Smuzhiyun #define __ASM_ARM_ARCH_MACRO_H__ 15*4882a593Smuzhiyun #ifdef __ASSEMBLY__ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <asm/arch/imx-regs.h> 18*4882a593Smuzhiyun #include <generated/asm-offsets.h> 19*4882a593Smuzhiyun #include <asm/macro.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * AIPS setup - Only setup MPROTx registers. 23*4882a593Smuzhiyun * The PACR default values are good. 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * Default argument values: 26*4882a593Smuzhiyun * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to 27*4882a593Smuzhiyun * user-mode. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun .macro init_aips mpr=0x77777777 30*4882a593Smuzhiyun ldr r0, =IMX_AIPS1_BASE 31*4882a593Smuzhiyun ldr r1, =\mpr 32*4882a593Smuzhiyun str r1, [r0, #AIPS_MPR_0_7] 33*4882a593Smuzhiyun str r1, [r0, #AIPS_MPR_8_15] 34*4882a593Smuzhiyun ldr r2, =IMX_AIPS2_BASE 35*4882a593Smuzhiyun str r1, [r2, #AIPS_MPR_0_7] 36*4882a593Smuzhiyun str r1, [r2, #AIPS_MPR_8_15] 37*4882a593Smuzhiyun .endm 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * MAX (Multi-Layer AHB Crossbar Switch) setup 41*4882a593Smuzhiyun * 42*4882a593Smuzhiyun * Default argument values: 43*4882a593Smuzhiyun * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA 44*4882a593Smuzhiyun * - SGPCR: always park on last master 45*4882a593Smuzhiyun * - MGPCR: restore default values 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun .macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000 48*4882a593Smuzhiyun ldr r0, =IMX_MAX_BASE 49*4882a593Smuzhiyun ldr r1, =\mpr 50*4882a593Smuzhiyun str r1, [r0, #MAX_MPR0] /* for S0 */ 51*4882a593Smuzhiyun str r1, [r0, #MAX_MPR1] /* for S1 */ 52*4882a593Smuzhiyun str r1, [r0, #MAX_MPR2] /* for S2 */ 53*4882a593Smuzhiyun str r1, [r0, #MAX_MPR3] /* for S3 */ 54*4882a593Smuzhiyun str r1, [r0, #MAX_MPR4] /* for S4 */ 55*4882a593Smuzhiyun ldr r1, =\sgpcr 56*4882a593Smuzhiyun str r1, [r0, #MAX_SGPCR0] /* for S0 */ 57*4882a593Smuzhiyun str r1, [r0, #MAX_SGPCR1] /* for S1 */ 58*4882a593Smuzhiyun str r1, [r0, #MAX_SGPCR2] /* for S2 */ 59*4882a593Smuzhiyun str r1, [r0, #MAX_SGPCR3] /* for S3 */ 60*4882a593Smuzhiyun str r1, [r0, #MAX_SGPCR4] /* for S4 */ 61*4882a593Smuzhiyun ldr r1, =\mgpcr 62*4882a593Smuzhiyun str r1, [r0, #MAX_MGPCR0] /* for M0 */ 63*4882a593Smuzhiyun str r1, [r0, #MAX_MGPCR1] /* for M1 */ 64*4882a593Smuzhiyun str r1, [r0, #MAX_MGPCR2] /* for M2 */ 65*4882a593Smuzhiyun str r1, [r0, #MAX_MGPCR3] /* for M3 */ 66*4882a593Smuzhiyun str r1, [r0, #MAX_MGPCR4] /* for M4 */ 67*4882a593Smuzhiyun .endm 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * M3IF setup 71*4882a593Smuzhiyun * 72*4882a593Smuzhiyun * Default argument values: 73*4882a593Smuzhiyun * - CTL: 74*4882a593Smuzhiyun * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 75*4882a593Smuzhiyun * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 76*4882a593Smuzhiyun * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 77*4882a593Smuzhiyun * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000 78*4882a593Smuzhiyun * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 79*4882a593Smuzhiyun * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000 80*4882a593Smuzhiyun * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000 81*4882a593Smuzhiyun * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 82*4882a593Smuzhiyun * ------------ 83*4882a593Smuzhiyun * 0x00000001 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun .macro init_m3if ctl=0x00000001 86*4882a593Smuzhiyun /* M3IF Control Register (M3IFCTL) */ 87*4882a593Smuzhiyun write32 IMX_M3IF_CTRL_BASE, \ctl 88*4882a593Smuzhiyun .endm 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 91*4882a593Smuzhiyun #endif /* __ASM_ARM_ARCH_MACRO_H__ */ 92