1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 4*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Derived from drivers/spi/mpc8xxx_spi.c 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __KW_SPI_H__ 12*4882a593Smuzhiyun #define __KW_SPI_H__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* SPI Registers on kirkwood SOC */ 15*4882a593Smuzhiyun struct kwspi_registers { 16*4882a593Smuzhiyun u32 ctrl; /* 0x10600 */ 17*4882a593Smuzhiyun u32 cfg; /* 0x10604 */ 18*4882a593Smuzhiyun u32 dout; /* 0x10608 */ 19*4882a593Smuzhiyun u32 din; /* 0x1060c */ 20*4882a593Smuzhiyun u32 irq_cause; /* 0x10610 */ 21*4882a593Smuzhiyun u32 irq_mask; /* 0x10614 */ 22*4882a593Smuzhiyun u32 timing1; /* 0x10618 */ 23*4882a593Smuzhiyun u32 timing2; /* 0x1061c */ 24*4882a593Smuzhiyun u32 dw_cfg; /* 0x10620 - Direct Write Configuration */ 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* They are used to define CONFIG_SYS_KW_SPI_MPP 28*4882a593Smuzhiyun * each of the below #defines selects which mpp is 29*4882a593Smuzhiyun * configured for each SPI signal in spi_claim_bus 30*4882a593Smuzhiyun * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1) 31*4882a593Smuzhiyun * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1) 32*4882a593Smuzhiyun * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1) 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun #define MOSI_MPP6 (1 << 0) 35*4882a593Smuzhiyun #define SCK_MPP10 (1 << 1) 36*4882a593Smuzhiyun #define MISO_MPP11 (1 << 2) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Control Register */ 39*4882a593Smuzhiyun #define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */ 40*4882a593Smuzhiyun #define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ 41*4882a593Smuzhiyun #define KWSPI_CS_SHIFT 2 /* chip select shift */ 42*4882a593Smuzhiyun #define KWSPI_CS_MASK 0x7 /* chip select mask */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Configuration Register */ 45*4882a593Smuzhiyun #define KWSPI_CLKPRESCL_MASK 0x1f 46*4882a593Smuzhiyun #define KWSPI_CLKPRESCL_MIN 0x12 47*4882a593Smuzhiyun #define KWSPI_XFERLEN_1BYTE 0 48*4882a593Smuzhiyun #define KWSPI_XFERLEN_2BYTE (1 << 5) 49*4882a593Smuzhiyun #define KWSPI_XFERLEN_MASK (1 << 5) 50*4882a593Smuzhiyun #define KWSPI_ADRLEN_1BYTE 0 51*4882a593Smuzhiyun #define KWSPI_ADRLEN_2BYTE (1 << 8) 52*4882a593Smuzhiyun #define KWSPI_ADRLEN_3BYTE (2 << 8) 53*4882a593Smuzhiyun #define KWSPI_ADRLEN_4BYTE (3 << 8) 54*4882a593Smuzhiyun #define KWSPI_ADRLEN_MASK (3 << 8) 55*4882a593Smuzhiyun #define KWSPI_CPOL (1 << 11) 56*4882a593Smuzhiyun #define KWSPI_CPHA (1 << 12) 57*4882a593Smuzhiyun #define KWSPI_TXLSBF (1 << 13) 58*4882a593Smuzhiyun #define KWSPI_RXLSBF (1 << 14) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Timing Parameters 1 Register */ 61*4882a593Smuzhiyun #define KW_SPI_TMISO_SAMPLE_OFFSET 6 62*4882a593Smuzhiyun #define KW_SPI_TMISO_SAMPLE_MASK (0x3 << KW_SPI_TMISO_SAMPLE_OFFSET) 63*4882a593Smuzhiyun #define KW_SPI_TMISO_SAMPLE_1 (1 << KW_SPI_TMISO_SAMPLE_OFFSET) 64*4882a593Smuzhiyun #define KW_SPI_TMISO_SAMPLE_2 (2 << KW_SPI_TMISO_SAMPLE_OFFSET) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ 67*4882a593Smuzhiyun #define KWSPI_IRQMASK 0 /* mask SPI interrupt */ 68*4882a593Smuzhiyun #define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define KWSPI_TIMEOUT 10000 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* __KW_SPI_H__ */ 73