1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 Carlo Caione <carlo@caione.org> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __SD_EMMC_H__ 8*4882a593Smuzhiyun #define __SD_EMMC_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <mmc.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define SDIO_PORT_A 0 13*4882a593Smuzhiyun #define SDIO_PORT_B 1 14*4882a593Smuzhiyun #define SDIO_PORT_C 2 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ 17*4882a593Smuzhiyun #define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MESON_SD_EMMC_CLOCK 0x00 20*4882a593Smuzhiyun #define CLK_MAX_DIV 63 21*4882a593Smuzhiyun #define CLK_SRC_24M (0 << 6) 22*4882a593Smuzhiyun #define CLK_SRC_DIV2 (1 << 6) 23*4882a593Smuzhiyun #define CLK_CO_PHASE_000 (0 << 8) 24*4882a593Smuzhiyun #define CLK_CO_PHASE_090 (1 << 8) 25*4882a593Smuzhiyun #define CLK_CO_PHASE_180 (2 << 8) 26*4882a593Smuzhiyun #define CLK_CO_PHASE_270 (3 << 8) 27*4882a593Smuzhiyun #define CLK_TX_PHASE_000 (0 << 10) 28*4882a593Smuzhiyun #define CLK_TX_PHASE_090 (1 << 10) 29*4882a593Smuzhiyun #define CLK_TX_PHASE_180 (2 << 10) 30*4882a593Smuzhiyun #define CLK_TX_PHASE_270 (3 << 10) 31*4882a593Smuzhiyun #define CLK_ALWAYS_ON BIT(24) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define MESON_SD_EMMC_CFG 0x44 34*4882a593Smuzhiyun #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 35*4882a593Smuzhiyun #define CFG_BUS_WIDTH_1 0 36*4882a593Smuzhiyun #define CFG_BUS_WIDTH_4 1 37*4882a593Smuzhiyun #define CFG_BUS_WIDTH_8 2 38*4882a593Smuzhiyun #define CFG_BL_LEN_MASK GENMASK(7, 4) 39*4882a593Smuzhiyun #define CFG_BL_LEN_SHIFT 4 40*4882a593Smuzhiyun #define CFG_BL_LEN_512 (9 << 4) 41*4882a593Smuzhiyun #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 42*4882a593Smuzhiyun #define CFG_RESP_TIMEOUT_256 (8 << 8) 43*4882a593Smuzhiyun #define CFG_RC_CC_MASK GENMASK(15, 12) 44*4882a593Smuzhiyun #define CFG_RC_CC_16 (4 << 12) 45*4882a593Smuzhiyun #define CFG_SDCLK_ALWAYS_ON BIT(18) 46*4882a593Smuzhiyun #define CFG_AUTO_CLK BIT(23) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define MESON_SD_EMMC_STATUS 0x48 49*4882a593Smuzhiyun #define STATUS_MASK GENMASK(15, 0) 50*4882a593Smuzhiyun #define STATUS_ERR_MASK GENMASK(12, 0) 51*4882a593Smuzhiyun #define STATUS_RXD_ERR_MASK GENMASK(7, 0) 52*4882a593Smuzhiyun #define STATUS_TXD_ERR BIT(8) 53*4882a593Smuzhiyun #define STATUS_DESC_ERR BIT(9) 54*4882a593Smuzhiyun #define STATUS_RESP_ERR BIT(10) 55*4882a593Smuzhiyun #define STATUS_RESP_TIMEOUT BIT(11) 56*4882a593Smuzhiyun #define STATUS_DESC_TIMEOUT BIT(12) 57*4882a593Smuzhiyun #define STATUS_END_OF_CHAIN BIT(13) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define MESON_SD_EMMC_IRQ_EN 0x4c 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define MESON_SD_EMMC_CMD_CFG 0x50 62*4882a593Smuzhiyun #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 63*4882a593Smuzhiyun #define CMD_CFG_BLOCK_MODE BIT(9) 64*4882a593Smuzhiyun #define CMD_CFG_R1B BIT(10) 65*4882a593Smuzhiyun #define CMD_CFG_END_OF_CHAIN BIT(11) 66*4882a593Smuzhiyun #define CMD_CFG_TIMEOUT_4S (12 << 12) 67*4882a593Smuzhiyun #define CMD_CFG_NO_RESP BIT(16) 68*4882a593Smuzhiyun #define CMD_CFG_DATA_IO BIT(18) 69*4882a593Smuzhiyun #define CMD_CFG_DATA_WR BIT(19) 70*4882a593Smuzhiyun #define CMD_CFG_RESP_NOCRC BIT(20) 71*4882a593Smuzhiyun #define CMD_CFG_RESP_128 BIT(21) 72*4882a593Smuzhiyun #define CMD_CFG_CMD_INDEX_SHIFT 24 73*4882a593Smuzhiyun #define CMD_CFG_OWNER BIT(31) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define MESON_SD_EMMC_CMD_ARG 0x54 76*4882a593Smuzhiyun #define MESON_SD_EMMC_CMD_DAT 0x58 77*4882a593Smuzhiyun #define MESON_SD_EMMC_CMD_RSP 0x5c 78*4882a593Smuzhiyun #define MESON_SD_EMMC_CMD_RSP1 0x60 79*4882a593Smuzhiyun #define MESON_SD_EMMC_CMD_RSP2 0x64 80*4882a593Smuzhiyun #define MESON_SD_EMMC_CMD_RSP3 0x68 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct meson_mmc_platdata { 83*4882a593Smuzhiyun struct mmc_config cfg; 84*4882a593Smuzhiyun struct mmc mmc; 85*4882a593Smuzhiyun void *regbase; 86*4882a593Smuzhiyun void *w_buf; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif 90