1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _LPC32XX_WDT_H 8*4882a593Smuzhiyun #define _LPC32XX_WDT_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/types.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Watchdog Timer Registers */ 13*4882a593Smuzhiyun struct wdt_regs { 14*4882a593Smuzhiyun u32 isr; /* Interrupt Status Register */ 15*4882a593Smuzhiyun u32 ctrl; /* Control Register */ 16*4882a593Smuzhiyun u32 counter; /* Counter Value Register */ 17*4882a593Smuzhiyun u32 mctrl; /* Match Control Register */ 18*4882a593Smuzhiyun u32 match0; /* Match 0 Register */ 19*4882a593Smuzhiyun u32 emr; /* External Match Control Register */ 20*4882a593Smuzhiyun u32 pulse; /* Reset Pulse Length Register */ 21*4882a593Smuzhiyun u32 res; /* Reset Source Register */ 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Watchdog Timer Control Register bits */ 25*4882a593Smuzhiyun #define WDTIM_CTRL_PAUSE_EN (1 << 2) 26*4882a593Smuzhiyun #define WDTIM_CTRL_RESET_COUNT (1 << 1) 27*4882a593Smuzhiyun #define WDTIM_CTRL_COUNT_ENAB (1 << 0) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Watchdog Timer Match Control Register bits */ 30*4882a593Smuzhiyun #define WDTIM_MCTRL_RESFRC2 (1 << 6) 31*4882a593Smuzhiyun #define WDTIM_MCTRL_RESFRC1 (1 << 5) 32*4882a593Smuzhiyun #define WDTIM_MCTRL_M_RES2 (1 << 4) 33*4882a593Smuzhiyun #define WDTIM_MCTRL_M_RES1 (1 << 3) 34*4882a593Smuzhiyun #define WDTIM_MCTRL_STOP_COUNT0 (1 << 2) 35*4882a593Smuzhiyun #define WDTIM_MCTRL_RESET_COUNT0 (1 << 1) 36*4882a593Smuzhiyun #define WDTIM_MCTRL_MR0_INT (1 << 0) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif /* _LPC32XX_WDT_H */ 39