1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _LPC32XX_UART_H 8*4882a593Smuzhiyun #define _LPC32XX_UART_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/types.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 14-clock UART Registers */ 13*4882a593Smuzhiyun struct hsuart_regs { 14*4882a593Smuzhiyun union { 15*4882a593Smuzhiyun u32 rx; /* Receiver FIFO */ 16*4882a593Smuzhiyun u32 tx; /* Transmitter FIFO */ 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun u32 level; /* FIFO Level Register */ 19*4882a593Smuzhiyun u32 iir; /* Interrupt ID Register */ 20*4882a593Smuzhiyun u32 ctrl; /* Control Register */ 21*4882a593Smuzhiyun u32 rate; /* Rate Control Register */ 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 14-clock UART Receiver FIFO Register bits */ 25*4882a593Smuzhiyun #define HSUART_RX_BREAK (1 << 10) 26*4882a593Smuzhiyun #define HSUART_RX_ERROR (1 << 9) 27*4882a593Smuzhiyun #define HSUART_RX_EMPTY (1 << 8) 28*4882a593Smuzhiyun #define HSUART_RX_DATA (0xff << 0) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 14-clock UART Level Register bits */ 31*4882a593Smuzhiyun #define HSUART_LEVEL_TX (0xff << 8) 32*4882a593Smuzhiyun #define HSUART_LEVEL_RX (0xff << 0) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* 14-clock UART Interrupt Identification Register bits */ 35*4882a593Smuzhiyun #define HSUART_IIR_TX_INT_SET (1 << 6) 36*4882a593Smuzhiyun #define HSUART_IIR_RX_OE (1 << 5) 37*4882a593Smuzhiyun #define HSUART_IIR_BRK (1 << 4) 38*4882a593Smuzhiyun #define HSUART_IIR_FE (1 << 3) 39*4882a593Smuzhiyun #define HSUART_IIR_RX_TIMEOUT (1 << 2) 40*4882a593Smuzhiyun #define HSUART_IIR_RX_TRIG (1 << 1) 41*4882a593Smuzhiyun #define HSUART_IIR_TX (1 << 0) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 14-clock UART Control Register bits */ 44*4882a593Smuzhiyun #define HSUART_CTRL_HRTS_INV (1 << 21) 45*4882a593Smuzhiyun #define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19) 46*4882a593Smuzhiyun #define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19) 47*4882a593Smuzhiyun #define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19) 48*4882a593Smuzhiyun #define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19) 49*4882a593Smuzhiyun #define HSUART_CTRL_HRTS_EN (1 << 18) 50*4882a593Smuzhiyun #define HSUART_CTRL_TMO_16 (0x3 << 16) 51*4882a593Smuzhiyun #define HSUART_CTRL_TMO_8 (0x2 << 16) 52*4882a593Smuzhiyun #define HSUART_CTRL_TMO_4 (0x1 << 16) 53*4882a593Smuzhiyun #define HSUART_CTRL_TMO_DISABLED (0x0 << 16) 54*4882a593Smuzhiyun #define HSUART_CTRL_HCTS_INV (1 << 15) 55*4882a593Smuzhiyun #define HSUART_CTRL_HCTS_EN (1 << 14) 56*4882a593Smuzhiyun #define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9) 57*4882a593Smuzhiyun #define HSUART_CTRL_HSU_BREAK (1 << 8) 58*4882a593Smuzhiyun #define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7) 59*4882a593Smuzhiyun #define HSUART_CTRL_HSU_RX_INT_EN (1 << 6) 60*4882a593Smuzhiyun #define HSUART_CTRL_HSU_TX_INT_EN (1 << 5) 61*4882a593Smuzhiyun #define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2) 62*4882a593Smuzhiyun #define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2) 63*4882a593Smuzhiyun #define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2) 64*4882a593Smuzhiyun #define HSUART_CTRL_HSU_RX_TRIG_8 (0x2 << 2) 65*4882a593Smuzhiyun #define HSUART_CTRL_HSU_RX_TRIG_4 (0x1 << 2) 66*4882a593Smuzhiyun #define HSUART_CTRL_HSU_RX_TRIG_1 (0x0 << 2) 67*4882a593Smuzhiyun #define HSUART_CTRL_HSU_TX_TRIG_16 (0x3 << 0) 68*4882a593Smuzhiyun #define HSUART_CTRL_HSU_TX_TRIG_8 (0x2 << 0) 69*4882a593Smuzhiyun #define HSUART_CTRL_HSU_TX_TRIG_4 (0x1 << 0) 70*4882a593Smuzhiyun #define HSUART_CTRL_HSU_TX_TRIG_0 (0x0 << 0) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* UART Control Registers */ 73*4882a593Smuzhiyun struct uart_ctrl_regs { 74*4882a593Smuzhiyun u32 ctrl; /* Control Register */ 75*4882a593Smuzhiyun u32 clkmode; /* Clock Mode Register */ 76*4882a593Smuzhiyun u32 loop; /* Loopback Control Register */ 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* UART Control Register bits */ 80*4882a593Smuzhiyun #define UART_CTRL_UART3_MD_CTRL (1 << 11) 81*4882a593Smuzhiyun #define UART_CTRL_HDPX_INV (1 << 10) 82*4882a593Smuzhiyun #define UART_CTRL_HDPX_EN (1 << 9) 83*4882a593Smuzhiyun #define UART_CTRL_UART6_IRDA (1 << 5) 84*4882a593Smuzhiyun #define UART_CTRL_IR_TX6_INV (1 << 4) 85*4882a593Smuzhiyun #define UART_CTRL_IR_RX6_INV (1 << 3) 86*4882a593Smuzhiyun #define UART_CTRL_IR_RX_LENGTH (1 << 2) 87*4882a593Smuzhiyun #define UART_CTRL_IR_TX_LENGTH (1 << 1) 88*4882a593Smuzhiyun #define UART_CTRL_UART5_USB_MODE (1 << 0) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* UART Clock Mode Register bits */ 91*4882a593Smuzhiyun #define UART_CLKMODE_STATX(n) (1 << ((n) + 16)) 92*4882a593Smuzhiyun #define UART_CLKMODE_STAT (1 << 14) 93*4882a593Smuzhiyun #define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2)) 94*4882a593Smuzhiyun #define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2)) 95*4882a593Smuzhiyun #define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2)) 96*4882a593Smuzhiyun #define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2)) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* UART Loopback Control Register bits */ 99*4882a593Smuzhiyun #define UART_LOOPBACK(n) (1 << ((n) - 1)) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif /* _LPC32XX_UART_H */ 102