1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _LPC32XX_TIMER_H 8*4882a593Smuzhiyun #define _LPC32XX_TIMER_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/types.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Timer/Counter Registers */ 13*4882a593Smuzhiyun struct timer_regs { 14*4882a593Smuzhiyun u32 ir; /* Interrupt Register */ 15*4882a593Smuzhiyun u32 tcr; /* Timer Control Register */ 16*4882a593Smuzhiyun u32 tc; /* Timer Counter */ 17*4882a593Smuzhiyun u32 pr; /* Prescale Register */ 18*4882a593Smuzhiyun u32 pc; /* Prescale Counter */ 19*4882a593Smuzhiyun u32 mcr; /* Match Control Register */ 20*4882a593Smuzhiyun u32 mr[4]; /* Match Registers */ 21*4882a593Smuzhiyun u32 ccr; /* Capture Control Register */ 22*4882a593Smuzhiyun u32 cr[4]; /* Capture Registers */ 23*4882a593Smuzhiyun u32 emr; /* External Match Register */ 24*4882a593Smuzhiyun u32 reserved[12]; 25*4882a593Smuzhiyun u32 ctcr; /* Count Control Register */ 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Timer/Counter Interrupt Register bits */ 29*4882a593Smuzhiyun #define TIMER_IR_CR(n) (1 << ((n) + 4)) 30*4882a593Smuzhiyun #define TIMER_IR_MR(n) (1 << (n)) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Timer/Counter Timer Control Register bits */ 33*4882a593Smuzhiyun #define TIMER_TCR_COUNTER_RESET (1 << 1) 34*4882a593Smuzhiyun #define TIMER_TCR_COUNTER_ENABLE (1 << 0) 35*4882a593Smuzhiyun #define TIMER_TCR_COUNTER_DISABLE (0 << 0) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Timer/Counter Match Control Register bits */ 38*4882a593Smuzhiyun #define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) 39*4882a593Smuzhiyun #define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) 40*4882a593Smuzhiyun #define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n))) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Timer/Counter Capture Control Register bits */ 43*4882a593Smuzhiyun #define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) 44*4882a593Smuzhiyun #define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) 45*4882a593Smuzhiyun #define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n))) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Timer/Counter External Match Register bits */ 48*4882a593Smuzhiyun #define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4)) 49*4882a593Smuzhiyun #define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) 50*4882a593Smuzhiyun #define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4)) 51*4882a593Smuzhiyun #define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4)) 52*4882a593Smuzhiyun #define TIMER_EMR_EM(n) (1 << (n)) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Timer/Counter Count Control Register bits */ 55*4882a593Smuzhiyun #define TIMER_CTCR_INPUT(n) ((n) << 2) 56*4882a593Smuzhiyun #define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) 57*4882a593Smuzhiyun #define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) 58*4882a593Smuzhiyun #define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) 59*4882a593Smuzhiyun #define TIMER_CTCR_MODE_TIMER (0x0 << 0) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif /* _LPC32XX_TIMER_H */ 62