1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * LPC32xx MUX interface 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2015 DENX Software Engineering GmbH 5*4882a593Smuzhiyun * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /** 11*4882a593Smuzhiyun * MUX register map for LPC32xx 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct mux_regs { 15*4882a593Smuzhiyun u32 reserved1[10]; 16*4882a593Smuzhiyun u32 p2_mux_set; 17*4882a593Smuzhiyun u32 p2_mux_clr; 18*4882a593Smuzhiyun u32 p2_mux_state; 19*4882a593Smuzhiyun u32 reserved2[51]; 20*4882a593Smuzhiyun u32 p_mux_set; 21*4882a593Smuzhiyun u32 p_mux_clr; 22*4882a593Smuzhiyun u32 p_mux_state; 23*4882a593Smuzhiyun u32 reserved3; 24*4882a593Smuzhiyun u32 p3_mux_set; 25*4882a593Smuzhiyun u32 p3_mux_clr; 26*4882a593Smuzhiyun u32 p3_mux_state; 27*4882a593Smuzhiyun u32 reserved4; 28*4882a593Smuzhiyun u32 p0_mux_set; 29*4882a593Smuzhiyun u32 p0_mux_clr; 30*4882a593Smuzhiyun u32 p0_mux_state; 31*4882a593Smuzhiyun u32 reserved5; 32*4882a593Smuzhiyun u32 p1_mux_set; 33*4882a593Smuzhiyun u32 p1_mux_clr; 34*4882a593Smuzhiyun u32 p1_mux_state; 35*4882a593Smuzhiyun }; 36