1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * LPC32xx GPIO interface macro for pin mapping. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2015 DENX Software Engineering GmbH 5*4882a593Smuzhiyun * Written-by: Sylvain Lemieux <slemieux@@tycoint.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _LPC32XX_GPIO_GRP_H 11*4882a593Smuzhiyun #define _LPC32XX_GPIO_GRP_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Macro to map the pin for the lpc32xx_gpio driver. 15*4882a593Smuzhiyun * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159; 16*4882a593Smuzhiyun * mapping is done per register, as group of 32. 17*4882a593Smuzhiyun * (see drivers/gpio/lpc32xx_gpio.c for details). 18*4882a593Smuzhiyun * - macros can be use with the following pins: 19*4882a593Smuzhiyun * P0.0 - P0.7 20*4882a593Smuzhiyun * P1.0 - P1.23 21*4882a593Smuzhiyun * P2.0 - P2.12 22*4882a593Smuzhiyun * P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28 23*4882a593Smuzhiyun * P3 GPO_0 - GPO_23 24*4882a593Smuzhiyun * P3 GPIO_0 - GPIO_5 (output register only) 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define LPC32XX_GPIO_P0_GRP 0 27*4882a593Smuzhiyun #define LPC32XX_GPIO_P1_GRP 32 28*4882a593Smuzhiyun #define LPC32XX_GPIO_P2_GRP 64 29*4882a593Smuzhiyun #define LPC32XX_GPO_P3_GRP 96 30*4882a593Smuzhiyun #define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25) 31*4882a593Smuzhiyun #define LPC32XX_GPI_P3_GRP 128 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * A specific GPIO can be selected with this macro 35*4882a593Smuzhiyun * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1) 36*4882a593Smuzhiyun * See the LPC32x0 User's guide for GPIO group numbers 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define LPC32XX_GPIO(x, y) ((x) + (y)) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif /* _LPC32XX_GPIO_GRP_H */ 41