1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * LPC32xx GPIO interface 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2014 DENX Software Engineering GmbH 5*4882a593Smuzhiyun * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /** 11*4882a593Smuzhiyun * GPIO Register map for LPC32xx 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct gpio_regs { 15*4882a593Smuzhiyun u32 p3_inp_state; 16*4882a593Smuzhiyun u32 p3_outp_set; 17*4882a593Smuzhiyun u32 p3_outp_clr; 18*4882a593Smuzhiyun u32 p3_outp_state; 19*4882a593Smuzhiyun /* Watch out! the following are shared between p2 and p3 */ 20*4882a593Smuzhiyun u32 p2_p3_dir_set; 21*4882a593Smuzhiyun u32 p2_p3_dir_clr; 22*4882a593Smuzhiyun u32 p2_p3_dir_state; 23*4882a593Smuzhiyun /* Now back to 'one register for one port' */ 24*4882a593Smuzhiyun u32 p2_inp_state; 25*4882a593Smuzhiyun u32 p2_outp_set; 26*4882a593Smuzhiyun u32 p2_outp_clr; 27*4882a593Smuzhiyun u32 reserved1[6]; 28*4882a593Smuzhiyun u32 p0_inp_state; 29*4882a593Smuzhiyun u32 p0_outp_set; 30*4882a593Smuzhiyun u32 p0_outp_clr; 31*4882a593Smuzhiyun u32 p0_outp_state; 32*4882a593Smuzhiyun u32 p0_dir_set; 33*4882a593Smuzhiyun u32 p0_dir_clr; 34*4882a593Smuzhiyun u32 p0_dir_state; 35*4882a593Smuzhiyun u32 reserved2; 36*4882a593Smuzhiyun u32 p1_inp_state; 37*4882a593Smuzhiyun u32 p1_outp_set; 38*4882a593Smuzhiyun u32 p1_outp_clr; 39*4882a593Smuzhiyun u32 p1_outp_state; 40*4882a593Smuzhiyun u32 p1_dir_set; 41*4882a593Smuzhiyun u32 p1_dir_clr; 42*4882a593Smuzhiyun u32 p1_dir_state; 43*4882a593Smuzhiyun }; 44