1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * LPC32xx DMA Controller Interface 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2008 by NXP Semiconductors 5*4882a593Smuzhiyun * @Author: Kevin Wells 6*4882a593Smuzhiyun * @Descr: Definitions for LPC3250 chip 7*4882a593Smuzhiyun * @References: NXP LPC3250 User's Guide 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _LPC32XX_DMA_H 13*4882a593Smuzhiyun #define _LPC32XX_DMA_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <common.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * DMA linked list structure used with a channel's LLI register; 19*4882a593Smuzhiyun * refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3 20*4882a593Smuzhiyun * tables 84, 85, 86 & 87 for details. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun struct lpc32xx_dmac_ll { 23*4882a593Smuzhiyun u32 dma_src; 24*4882a593Smuzhiyun u32 dma_dest; 25*4882a593Smuzhiyun u32 next_lli; 26*4882a593Smuzhiyun u32 next_ctrl; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* control register definitions */ 30*4882a593Smuzhiyun #define DMAC_CHAN_INT_TC_EN (1 << 31) /* channel terminal count interrupt */ 31*4882a593Smuzhiyun #define DMAC_CHAN_DEST_AUTOINC (1 << 27) /* automatic destination increment */ 32*4882a593Smuzhiyun #define DMAC_CHAN_SRC_AUTOINC (1 << 26) /* automatic source increment */ 33*4882a593Smuzhiyun #define DMAC_CHAN_DEST_AHB1 (1 << 25) /* AHB1 master for dest. transfer */ 34*4882a593Smuzhiyun #define DMAC_CHAN_DEST_WIDTH_32 (1 << 22) /* Destination data width selection */ 35*4882a593Smuzhiyun #define DMAC_CHAN_SRC_WIDTH_32 (1 << 19) /* Source data width selection */ 36*4882a593Smuzhiyun #define DMAC_CHAN_DEST_BURST_1 0 37*4882a593Smuzhiyun #define DMAC_CHAN_DEST_BURST_4 (1 << 15) /* Destination data burst size */ 38*4882a593Smuzhiyun #define DMAC_CHAN_SRC_BURST_1 0 39*4882a593Smuzhiyun #define DMAC_CHAN_SRC_BURST_4 (1 << 12) /* Source data burst size */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * config_ch register definitions 43*4882a593Smuzhiyun * DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller 44*4882a593Smuzhiyun * DMAC_DEST_PERIP: Macro for loading destination peripheral 45*4882a593Smuzhiyun * DMAC_SRC_PERIP: Macro for loading source peripheral 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun #define DMAC_CHAN_FLOW_D_M2P (0x1 << 11) 48*4882a593Smuzhiyun #define DMAC_CHAN_FLOW_D_P2M (0x2 << 11) 49*4882a593Smuzhiyun #define DMAC_DEST_PERIP(n) (((n) & 0x1F) << 6) 50*4882a593Smuzhiyun #define DMAC_SRC_PERIP(n) (((n) & 0x1F) << 1) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * config_ch register definitions 54*4882a593Smuzhiyun * (source and destination peripheral ID numbers). 55*4882a593Smuzhiyun * These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define DMA_PERID_NAND1 1 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Channel enable bit */ 60*4882a593Smuzhiyun #define DMAC_CHAN_ENABLE (1 << 0) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun int lpc32xx_dma_get_channel(void); 63*4882a593Smuzhiyun int lpc32xx_dma_start_xfer(unsigned int channel, 64*4882a593Smuzhiyun const struct lpc32xx_dmac_ll *desc, u32 config); 65*4882a593Smuzhiyun int lpc32xx_dma_wait_status(unsigned int channel); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* _LPC32XX_DMA_H */ 68