1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Linaro 3*4882a593Smuzhiyun * Peter Griffin <peter.griffin@linaro.org> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARM_ARCH_PINMUX_H 9*4882a593Smuzhiyun #define __ASM_ARM_ARCH_PINMUX_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "periph.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* iomg bit definition */ 15*4882a593Smuzhiyun #define MUX_M0 0 16*4882a593Smuzhiyun #define MUX_M1 1 17*4882a593Smuzhiyun #define MUX_M2 2 18*4882a593Smuzhiyun #define MUX_M3 3 19*4882a593Smuzhiyun #define MUX_M4 4 20*4882a593Smuzhiyun #define MUX_M5 5 21*4882a593Smuzhiyun #define MUX_M6 6 22*4882a593Smuzhiyun #define MUX_M7 7 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* iocg bit definition */ 25*4882a593Smuzhiyun #define PULL_MASK (3) 26*4882a593Smuzhiyun #define PULL_DIS (0) 27*4882a593Smuzhiyun #define PULL_UP (1 << 0) 28*4882a593Smuzhiyun #define PULL_DOWN (1 << 1) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* drive strength definition */ 31*4882a593Smuzhiyun #define DRIVE_MASK (7 << 4) 32*4882a593Smuzhiyun #define DRIVE1_02MA (0 << 4) 33*4882a593Smuzhiyun #define DRIVE1_04MA (1 << 4) 34*4882a593Smuzhiyun #define DRIVE1_08MA (2 << 4) 35*4882a593Smuzhiyun #define DRIVE1_10MA (3 << 4) 36*4882a593Smuzhiyun #define DRIVE2_02MA (0 << 4) 37*4882a593Smuzhiyun #define DRIVE2_04MA (1 << 4) 38*4882a593Smuzhiyun #define DRIVE2_08MA (2 << 4) 39*4882a593Smuzhiyun #define DRIVE2_10MA (3 << 4) 40*4882a593Smuzhiyun #define DRIVE3_04MA (0 << 4) 41*4882a593Smuzhiyun #define DRIVE3_08MA (1 << 4) 42*4882a593Smuzhiyun #define DRIVE3_12MA (2 << 4) 43*4882a593Smuzhiyun #define DRIVE3_16MA (3 << 4) 44*4882a593Smuzhiyun #define DRIVE3_20MA (4 << 4) 45*4882a593Smuzhiyun #define DRIVE3_24MA (5 << 4) 46*4882a593Smuzhiyun #define DRIVE3_32MA (6 << 4) 47*4882a593Smuzhiyun #define DRIVE3_40MA (7 << 4) 48*4882a593Smuzhiyun #define DRIVE4_02MA (0 << 4) 49*4882a593Smuzhiyun #define DRIVE4_04MA (2 << 4) 50*4882a593Smuzhiyun #define DRIVE4_08MA (4 << 4) 51*4882a593Smuzhiyun #define DRIVE4_10MA (6 << 4) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define HI6220_PINMUX0_BASE 0xf7010000 54*4882a593Smuzhiyun #define HI6220_PINMUX1_BASE 0xf7010800 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* maybe more registers, but highest used is 123 */ 59*4882a593Smuzhiyun #define REG_NUM 123 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun struct hi6220_pinmux0_regs { 62*4882a593Smuzhiyun uint32_t iomg[REG_NUM]; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct hi6220_pinmux1_regs { 66*4882a593Smuzhiyun uint32_t iocfg[REG_NUM]; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /** 72*4882a593Smuzhiyun * Configures the pinmux for a particular peripheral. 73*4882a593Smuzhiyun * 74*4882a593Smuzhiyun * This function will configure the peripheral pinmux along with 75*4882a593Smuzhiyun * pull-up/down and drive strength. 76*4882a593Smuzhiyun * 77*4882a593Smuzhiyun * @param peripheral peripheral to be configured 78*4882a593Smuzhiyun * @return 0 if ok, -1 on error (e.g. unsupported peripheral) 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun int hi6220_pinmux_config(int peripheral); 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif 83