1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Linaro 3*4882a593Smuzhiyun * Peter Griffin <peter.griffin@linaro.org> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARM_ARCH_PERIPH_H 9*4882a593Smuzhiyun #define __ASM_ARM_ARCH_PERIPH_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Peripherals required for pinmux configuration. List will 13*4882a593Smuzhiyun * grow with support for more devices getting added. 14*4882a593Smuzhiyun * Numbering based on interrupt table. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun enum periph_id { 18*4882a593Smuzhiyun PERIPH_ID_UART0 = 36, 19*4882a593Smuzhiyun PERIPH_ID_UART1, 20*4882a593Smuzhiyun PERIPH_ID_UART2, 21*4882a593Smuzhiyun PERIPH_ID_UART3, 22*4882a593Smuzhiyun PERIPH_ID_UART4, 23*4882a593Smuzhiyun PERIPH_ID_UART5, 24*4882a593Smuzhiyun PERIPH_ID_SDMMC0 = 72, 25*4882a593Smuzhiyun PERIPH_ID_SDMMC1, 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun PERIPH_ID_NONE = -1, 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #endif /* __ASM_ARM_ARCH_PERIPH_H */ 31