1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2017 Linaro 3*4882a593Smuzhiyun * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __HI3798cv200_H__ 9*4882a593Smuzhiyun #define __HI3798cv200_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define REG_BASE_PERI_CTRL 0xF8A20000 12*4882a593Smuzhiyun #define REG_BASE_CRG 0xF8A22000 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* DEVICES */ 15*4882a593Smuzhiyun #define REG_BASE_MCI 0xF9830000 16*4882a593Smuzhiyun #define REG_BASE_UART0 0xF8B00000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* PERI control registers (4KB) */ 19*4882a593Smuzhiyun /* USB2 PHY01 configuration register */ 20*4882a593Smuzhiyun #define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* PERI CRG registers (4KB) */ 23*4882a593Smuzhiyun /* USB2 CTRL0 clock and soft reset */ 24*4882a593Smuzhiyun #define PERI_CRG46 (REG_BASE_CRG + 0xb8) 25*4882a593Smuzhiyun #define USB2_BUS_CKEN (1<<0) 26*4882a593Smuzhiyun #define USB2_OHCI48M_CKEN (1<<1) 27*4882a593Smuzhiyun #define USB2_OHCI12M_CKEN (1<<2) 28*4882a593Smuzhiyun #define USB2_OTG_UTMI_CKEN (1<<3) 29*4882a593Smuzhiyun #define USB2_HST_PHY_CKEN (1<<4) 30*4882a593Smuzhiyun #define USB2_UTMI0_CKEN (1<<5) 31*4882a593Smuzhiyun #define USB2_BUS_SRST_REQ (1<<12) 32*4882a593Smuzhiyun #define USB2_UTMI0_SRST_REQ (1<<13) 33*4882a593Smuzhiyun #define USB2_HST_PHY_SYST_REQ (1<<16) 34*4882a593Smuzhiyun #define USB2_OTG_PHY_SYST_REQ (1<<17) 35*4882a593Smuzhiyun #define USB2_CLK48_SEL (1<<20) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* USB2 PHY clock and soft reset */ 38*4882a593Smuzhiyun #define PERI_CRG47 (REG_BASE_CRG + 0xbc) 39*4882a593Smuzhiyun #define USB2_PHY01_REF_CKEN (1 << 0) 40*4882a593Smuzhiyun #define USB2_PHY2_REF_CKEN (1 << 2) 41*4882a593Smuzhiyun #define USB2_PHY01_SRST_REQ (1 << 4) 42*4882a593Smuzhiyun #define USB2_PHY2_SRST_REQ (1 << 6) 43*4882a593Smuzhiyun #define USB2_PHY01_SRST_TREQ0 (1 << 8) 44*4882a593Smuzhiyun #define USB2_PHY01_SRST_TREQ1 (1 << 9) 45*4882a593Smuzhiyun #define USB2_PHY2_SRST_TREQ (1 << 10) 46*4882a593Smuzhiyun #define USB2_PHY01_REFCLK_SEL (1 << 12) 47*4882a593Smuzhiyun #define USB2_PHY2_REFCLK_SEL (1 << 14) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif 51