1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2017 NXP 3*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 9*4882a593Smuzhiyun #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun #ifdef CONFIG_FSL_LSCH2 14*4882a593Smuzhiyun #include <asm/arch/immap_lsch2.h> 15*4882a593Smuzhiyun #endif 16*4882a593Smuzhiyun #ifdef CONFIG_FSL_LSCH3 17*4882a593Smuzhiyun #include <asm/arch/immap_lsch3.h> 18*4882a593Smuzhiyun #endif 19*4882a593Smuzhiyun #endif 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE 22*4882a593Smuzhiyun #define gur_in32(a) in_le32(a) 23*4882a593Smuzhiyun #define gur_out32(a, v) out_le32(a, v) 24*4882a593Smuzhiyun #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) 25*4882a593Smuzhiyun #define gur_in32(a) in_be32(a) 26*4882a593Smuzhiyun #define gur_out32(a, v) out_be32(a, v) 27*4882a593Smuzhiyun #endif 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE 30*4882a593Smuzhiyun #define scfg_in32(a) in_le32(a) 31*4882a593Smuzhiyun #define scfg_out32(a, v) out_le32(a, v) 32*4882a593Smuzhiyun #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) 33*4882a593Smuzhiyun #define scfg_in32(a) in_be32(a) 34*4882a593Smuzhiyun #define scfg_out32(a, v) out_be32(a, v) 35*4882a593Smuzhiyun #endif 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_PEX_LUT_LE 38*4882a593Smuzhiyun #define pex_lut_in32(a) in_le32(a) 39*4882a593Smuzhiyun #define pex_lut_out32(a, v) out_le32(a, v) 40*4882a593Smuzhiyun #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) 41*4882a593Smuzhiyun #define pex_lut_in32(a) in_be32(a) 42*4882a593Smuzhiyun #define pex_lut_out32(a, v) out_be32(a, v) 43*4882a593Smuzhiyun #endif 44*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 45*4882a593Smuzhiyun struct cpu_type { 46*4882a593Smuzhiyun char name[15]; 47*4882a593Smuzhiyun u32 soc_ver; 48*4882a593Smuzhiyun u32 num_cores; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CPU_TYPE_ENTRY(n, v, nc) \ 52*4882a593Smuzhiyun { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun #define SVR_WO_E 0xFFFFFE 55*4882a593Smuzhiyun #define SVR_LS1012A 0x870400 56*4882a593Smuzhiyun #define SVR_LS1043A 0x879200 57*4882a593Smuzhiyun #define SVR_LS1023A 0x879208 58*4882a593Smuzhiyun #define SVR_LS1046A 0x870700 59*4882a593Smuzhiyun #define SVR_LS1026A 0x870708 60*4882a593Smuzhiyun #define SVR_LS2045A 0x870120 61*4882a593Smuzhiyun #define SVR_LS2080A 0x870110 62*4882a593Smuzhiyun #define SVR_LS2085A 0x870100 63*4882a593Smuzhiyun #define SVR_LS2040A 0x870130 64*4882a593Smuzhiyun #define SVR_LS2088A 0x870900 65*4882a593Smuzhiyun #define SVR_LS2084A 0x870910 66*4882a593Smuzhiyun #define SVR_LS2048A 0x870920 67*4882a593Smuzhiyun #define SVR_LS2044A 0x870930 68*4882a593Smuzhiyun #define SVR_LS2081A 0x870918 69*4882a593Smuzhiyun #define SVR_LS2041A 0x870914 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 72*4882a593Smuzhiyun #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 73*4882a593Smuzhiyun #define SVR_REV(svr) (((svr) >> 0) & 0xff) 74*4882a593Smuzhiyun #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) 75*4882a593Smuzhiyun #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) 76*4882a593Smuzhiyun #define IS_SVR_REV(svr, maj, min) \ 77*4882a593Smuzhiyun ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) 78*4882a593Smuzhiyun #define SVR_DEV(svr) ((svr) >> 8) 79*4882a593Smuzhiyun #define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev)) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* ahci port register default value */ 82*4882a593Smuzhiyun #define AHCI_PORT_PHY_1_CFG 0xa003fffe 83*4882a593Smuzhiyun #define AHCI_PORT_TRANS_CFG 0x08000029 84*4882a593Smuzhiyun #define AHCI_PORT_AXICC_CFG 0x3fffffff 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 87*4882a593Smuzhiyun /* AHCI (sata) register map */ 88*4882a593Smuzhiyun struct ccsr_ahci { 89*4882a593Smuzhiyun u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ 90*4882a593Smuzhiyun u32 pcfg; /* port config */ 91*4882a593Smuzhiyun u32 ppcfg; /* port phy1 config */ 92*4882a593Smuzhiyun u32 pp2c; /* port phy2 config */ 93*4882a593Smuzhiyun u32 pp3c; /* port phy3 config */ 94*4882a593Smuzhiyun u32 pp4c; /* port phy4 config */ 95*4882a593Smuzhiyun u32 pp5c; /* port phy5 config */ 96*4882a593Smuzhiyun u32 axicc; /* AXI cache control */ 97*4882a593Smuzhiyun u32 paxic; /* port AXI config */ 98*4882a593Smuzhiyun u32 axipc; /* AXI PROT control */ 99*4882a593Smuzhiyun u32 ptc; /* port Trans Config */ 100*4882a593Smuzhiyun u32 pts; /* port Trans Status */ 101*4882a593Smuzhiyun u32 plc; /* port link config */ 102*4882a593Smuzhiyun u32 plc1; /* port link config1 */ 103*4882a593Smuzhiyun u32 plc2; /* port link config2 */ 104*4882a593Smuzhiyun u32 pls; /* port link status */ 105*4882a593Smuzhiyun u32 pls1; /* port link status1 */ 106*4882a593Smuzhiyun u32 pcmdc; /* port CMD config */ 107*4882a593Smuzhiyun u32 ppcs; /* port phy control status */ 108*4882a593Smuzhiyun u32 pberr; /* port 0/1 BIST error */ 109*4882a593Smuzhiyun u32 cmds; /* port 0/1 CMD status error */ 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #ifdef CONFIG_FSL_LSCH3 113*4882a593Smuzhiyun void fsl_lsch3_early_init_f(void); 114*4882a593Smuzhiyun #elif defined(CONFIG_FSL_LSCH2) 115*4882a593Smuzhiyun void fsl_lsch2_early_init_f(void); 116*4882a593Smuzhiyun int setup_chip_volt(void); 117*4882a593Smuzhiyun /* Setup core vdd in unit mV */ 118*4882a593Smuzhiyun int board_setup_core_volt(u32 vdd); 119*4882a593Smuzhiyun #endif 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun void cpu_name(char *name); 122*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 123*4882a593Smuzhiyun void erratum_a009635(void); 124*4882a593Smuzhiyun #endif 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 127*4882a593Smuzhiyun void erratum_a010315(void); 128*4882a593Smuzhiyun #endif 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun bool soc_has_dp_ddr(void); 131*4882a593Smuzhiyun bool soc_has_aiop(void); 132*4882a593Smuzhiyun #endif 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ 135