1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014-2015, Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _FSL_LAYERSCAPE_MP_H 8*4882a593Smuzhiyun #define _FSL_LAYERSCAPE_MP_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * Each spin table element is defined as 12*4882a593Smuzhiyun * struct { 13*4882a593Smuzhiyun * uint64_t entry_addr; 14*4882a593Smuzhiyun * uint64_t status; 15*4882a593Smuzhiyun * uint64_t lpid; 16*4882a593Smuzhiyun * uint64_t arch_comp; 17*4882a593Smuzhiyun * }; 18*4882a593Smuzhiyun * we pad this struct to 64 bytes so each entry is in its own cacheline 19*4882a593Smuzhiyun * the actual spin table is an array of these structures 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 22*4882a593Smuzhiyun #define SPIN_TABLE_ELEM_STATUS_IDX 1 23*4882a593Smuzhiyun #define SPIN_TABLE_ELEM_LPID_IDX 2 24*4882a593Smuzhiyun /* compare os arch and cpu arch */ 25*4882a593Smuzhiyun #define SPIN_TABLE_ELEM_ARCH_COMP_IDX 3 26*4882a593Smuzhiyun #define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ 27*4882a593Smuzhiyun #define SPIN_TABLE_ELEM_SIZE 64 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* os arch is same as cpu arch */ 30*4882a593Smuzhiyun #define OS_ARCH_SAME 0 31*4882a593Smuzhiyun /* os arch is different from cpu arch */ 32*4882a593Smuzhiyun #define OS_ARCH_DIFF 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define id_to_core(x) ((x & 3) | (x >> 6)) 35*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 36*4882a593Smuzhiyun extern u64 __spin_table[]; 37*4882a593Smuzhiyun extern u64 __real_cntfrq; 38*4882a593Smuzhiyun extern u64 *secondary_boot_code; 39*4882a593Smuzhiyun extern size_t __secondary_boot_code_size; 40*4882a593Smuzhiyun #ifdef CONFIG_MP 41*4882a593Smuzhiyun int fsl_layerscape_wake_seconday_cores(void); 42*4882a593Smuzhiyun #else fsl_layerscape_wake_seconday_cores(void)43*4882a593Smuzhiyunstatic inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } 44*4882a593Smuzhiyun #endif 45*4882a593Smuzhiyun void *get_spin_tbl_addr(void); 46*4882a593Smuzhiyun phys_addr_t determine_mp_bootpg(void); 47*4882a593Smuzhiyun void secondary_boot_func(void); 48*4882a593Smuzhiyun int is_core_online(u64 cpu_id); 49*4882a593Smuzhiyun u32 cpu_pos_mask(void); 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif /* _FSL_LAYERSCAPE_MP_H */ 53