1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __FSL_SERDES_H__ 8*4882a593Smuzhiyun #define __FSL_SERDES_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <config.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifdef CONFIG_ARCH_LS2080A 13*4882a593Smuzhiyun enum srds_prtcl { 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Nobody will check whether the device 'NONE' has been configured, 16*4882a593Smuzhiyun * So use it to indicate if the serdes_prtcl_map has been initialized. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun NONE = 0, 19*4882a593Smuzhiyun PCIE1, 20*4882a593Smuzhiyun PCIE2, 21*4882a593Smuzhiyun PCIE3, 22*4882a593Smuzhiyun PCIE4, 23*4882a593Smuzhiyun SATA1, 24*4882a593Smuzhiyun SATA2, 25*4882a593Smuzhiyun XAUI1, 26*4882a593Smuzhiyun XAUI2, 27*4882a593Smuzhiyun XFI1, 28*4882a593Smuzhiyun XFI2, 29*4882a593Smuzhiyun XFI3, 30*4882a593Smuzhiyun XFI4, 31*4882a593Smuzhiyun XFI5, 32*4882a593Smuzhiyun XFI6, 33*4882a593Smuzhiyun XFI7, 34*4882a593Smuzhiyun XFI8, 35*4882a593Smuzhiyun SGMII1, 36*4882a593Smuzhiyun SGMII2, 37*4882a593Smuzhiyun SGMII3, 38*4882a593Smuzhiyun SGMII4, 39*4882a593Smuzhiyun SGMII5, 40*4882a593Smuzhiyun SGMII6, 41*4882a593Smuzhiyun SGMII7, 42*4882a593Smuzhiyun SGMII8, 43*4882a593Smuzhiyun SGMII9, 44*4882a593Smuzhiyun SGMII10, 45*4882a593Smuzhiyun SGMII11, 46*4882a593Smuzhiyun SGMII12, 47*4882a593Smuzhiyun SGMII13, 48*4882a593Smuzhiyun SGMII14, 49*4882a593Smuzhiyun SGMII15, 50*4882a593Smuzhiyun SGMII16, 51*4882a593Smuzhiyun QSGMII_A, 52*4882a593Smuzhiyun QSGMII_B, 53*4882a593Smuzhiyun QSGMII_C, 54*4882a593Smuzhiyun QSGMII_D, 55*4882a593Smuzhiyun SERDES_PRCTL_COUNT 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun enum srds { 59*4882a593Smuzhiyun FSL_SRDS_1 = 0, 60*4882a593Smuzhiyun FSL_SRDS_2 = 1, 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun #elif defined(CONFIG_FSL_LSCH2) 63*4882a593Smuzhiyun enum srds_prtcl { 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * Nobody will check whether the device 'NONE' has been configured, 66*4882a593Smuzhiyun * So use it to indicate if the serdes_prtcl_map has been initialized. 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun NONE = 0, 69*4882a593Smuzhiyun PCIE1, 70*4882a593Smuzhiyun PCIE2, 71*4882a593Smuzhiyun PCIE3, 72*4882a593Smuzhiyun PCIE4, 73*4882a593Smuzhiyun SATA1, 74*4882a593Smuzhiyun SATA2, 75*4882a593Smuzhiyun SRIO1, 76*4882a593Smuzhiyun SRIO2, 77*4882a593Smuzhiyun SGMII_FM1_DTSEC1, 78*4882a593Smuzhiyun SGMII_FM1_DTSEC2, 79*4882a593Smuzhiyun SGMII_FM1_DTSEC3, 80*4882a593Smuzhiyun SGMII_FM1_DTSEC4, 81*4882a593Smuzhiyun SGMII_FM1_DTSEC5, 82*4882a593Smuzhiyun SGMII_FM1_DTSEC6, 83*4882a593Smuzhiyun SGMII_FM1_DTSEC9, 84*4882a593Smuzhiyun SGMII_FM1_DTSEC10, 85*4882a593Smuzhiyun SGMII_FM2_DTSEC1, 86*4882a593Smuzhiyun SGMII_FM2_DTSEC2, 87*4882a593Smuzhiyun SGMII_FM2_DTSEC3, 88*4882a593Smuzhiyun SGMII_FM2_DTSEC4, 89*4882a593Smuzhiyun SGMII_FM2_DTSEC5, 90*4882a593Smuzhiyun SGMII_FM2_DTSEC6, 91*4882a593Smuzhiyun SGMII_FM2_DTSEC9, 92*4882a593Smuzhiyun SGMII_FM2_DTSEC10, 93*4882a593Smuzhiyun SGMII_TSEC1, 94*4882a593Smuzhiyun SGMII_TSEC2, 95*4882a593Smuzhiyun SGMII_TSEC3, 96*4882a593Smuzhiyun SGMII_TSEC4, 97*4882a593Smuzhiyun XAUI_FM1, 98*4882a593Smuzhiyun XAUI_FM2, 99*4882a593Smuzhiyun AURORA, 100*4882a593Smuzhiyun CPRI1, 101*4882a593Smuzhiyun CPRI2, 102*4882a593Smuzhiyun CPRI3, 103*4882a593Smuzhiyun CPRI4, 104*4882a593Smuzhiyun CPRI5, 105*4882a593Smuzhiyun CPRI6, 106*4882a593Smuzhiyun CPRI7, 107*4882a593Smuzhiyun CPRI8, 108*4882a593Smuzhiyun XAUI_FM1_MAC9, 109*4882a593Smuzhiyun XAUI_FM1_MAC10, 110*4882a593Smuzhiyun XAUI_FM2_MAC9, 111*4882a593Smuzhiyun XAUI_FM2_MAC10, 112*4882a593Smuzhiyun HIGIG_FM1_MAC9, 113*4882a593Smuzhiyun HIGIG_FM1_MAC10, 114*4882a593Smuzhiyun HIGIG_FM2_MAC9, 115*4882a593Smuzhiyun HIGIG_FM2_MAC10, 116*4882a593Smuzhiyun QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */ 117*4882a593Smuzhiyun QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ 118*4882a593Smuzhiyun QSGMII_FM2_A, 119*4882a593Smuzhiyun QSGMII_FM2_B, 120*4882a593Smuzhiyun XFI_FM1_MAC1, 121*4882a593Smuzhiyun XFI_FM1_MAC2, 122*4882a593Smuzhiyun XFI_FM1_MAC9, 123*4882a593Smuzhiyun XFI_FM1_MAC10, 124*4882a593Smuzhiyun XFI_FM2_MAC9, 125*4882a593Smuzhiyun XFI_FM2_MAC10, 126*4882a593Smuzhiyun INTERLAKEN, 127*4882a593Smuzhiyun QSGMII_SW1_A, /* Indicates ports on L2 Switch */ 128*4882a593Smuzhiyun QSGMII_SW1_B, 129*4882a593Smuzhiyun SGMII_2500_FM1_DTSEC1, 130*4882a593Smuzhiyun SGMII_2500_FM1_DTSEC2, 131*4882a593Smuzhiyun SGMII_2500_FM1_DTSEC3, 132*4882a593Smuzhiyun SGMII_2500_FM1_DTSEC4, 133*4882a593Smuzhiyun SGMII_2500_FM1_DTSEC5, 134*4882a593Smuzhiyun SGMII_2500_FM1_DTSEC6, 135*4882a593Smuzhiyun SGMII_2500_FM1_DTSEC9, 136*4882a593Smuzhiyun SGMII_2500_FM1_DTSEC10, 137*4882a593Smuzhiyun SGMII_2500_FM2_DTSEC1, 138*4882a593Smuzhiyun SGMII_2500_FM2_DTSEC2, 139*4882a593Smuzhiyun SGMII_2500_FM2_DTSEC3, 140*4882a593Smuzhiyun SGMII_2500_FM2_DTSEC4, 141*4882a593Smuzhiyun SGMII_2500_FM2_DTSEC5, 142*4882a593Smuzhiyun SGMII_2500_FM2_DTSEC6, 143*4882a593Smuzhiyun SGMII_2500_FM2_DTSEC9, 144*4882a593Smuzhiyun SGMII_2500_FM2_DTSEC10, 145*4882a593Smuzhiyun TX_CLK, 146*4882a593Smuzhiyun SERDES_PRCTL_COUNT 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun enum srds { 150*4882a593Smuzhiyun FSL_SRDS_1 = 0, 151*4882a593Smuzhiyun FSL_SRDS_2 = 1, 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #endif 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun int is_serdes_configured(enum srds_prtcl device); 157*4882a593Smuzhiyun void fsl_serdes_init(void); 158*4882a593Smuzhiyun int serdes_get_first_lane(u32 sd, enum srds_prtcl device); 159*4882a593Smuzhiyun enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); 160*4882a593Smuzhiyun int is_serdes_prtcl_valid(int serdes, u32 prtcl); 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #ifdef CONFIG_FSL_LSCH2 163*4882a593Smuzhiyun const char *serdes_clock_to_string(u32 clock); 164*4882a593Smuzhiyun int get_serdes_protocol(void); 165*4882a593Smuzhiyun #ifdef CONFIG_SYS_HAS_SERDES 166*4882a593Smuzhiyun /* Get the volt of SVDD in unit mV */ 167*4882a593Smuzhiyun int get_serdes_volt(void); 168*4882a593Smuzhiyun /* Set the volt of SVDD in unit mV */ 169*4882a593Smuzhiyun int set_serdes_volt(int svdd); 170*4882a593Smuzhiyun /* The target volt of SVDD in unit mV */ 171*4882a593Smuzhiyun int setup_serdes_volt(u32 svdd); 172*4882a593Smuzhiyun #endif 173*4882a593Smuzhiyun #endif 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #endif /* __FSL_SERDES_H__ */ 176