1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Broadcom Corporation. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ARCH_BCM235XX_SYSMAP_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define BSC1_BASE_ADDR 0x3e016000 10*4882a593Smuzhiyun #define BSC2_BASE_ADDR 0x3e017000 11*4882a593Smuzhiyun #define BSC3_BASE_ADDR 0x3e018000 12*4882a593Smuzhiyun #define GPIO2_BASE_ADDR 0x35003000 13*4882a593Smuzhiyun #define HSOTG_BASE_ADDR 0x3f120000 14*4882a593Smuzhiyun #define HSOTG_CTRL_BASE_ADDR 0x3f130000 15*4882a593Smuzhiyun #define KONA_MST_CLK_BASE_ADDR 0x3f001000 16*4882a593Smuzhiyun #define KONA_SLV_CLK_BASE_ADDR 0x3e011000 17*4882a593Smuzhiyun #define PMU_BSC_BASE_ADDR 0x3500d000 18*4882a593Smuzhiyun #define SDIO1_BASE_ADDR 0x3f180000 19*4882a593Smuzhiyun #define SDIO2_BASE_ADDR 0x3f190000 20*4882a593Smuzhiyun #define SDIO3_BASE_ADDR 0x3f1a0000 21*4882a593Smuzhiyun #define SDIO4_BASE_ADDR 0x3f1b0000 22*4882a593Smuzhiyun #define TIMER_BASE_ADDR 0x3e00d000 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define HSOTG_DCTL_OFFSET 0x00000804 25*4882a593Smuzhiyun #define HSOTG_DCTL_SFTDISCON_MASK 0x00000002 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008 28*4882a593Smuzhiyun #define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002 29*4882a593Smuzhiyun #define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif 32