1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_TIMER_H 7*4882a593Smuzhiyun #define _ASM_ARCH_TIMER_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* Each timer has 4 control bits in ctrl1 register. 10*4882a593Smuzhiyun * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on, 11*4882a593Smuzhiyun * such that timer X uses bits (4 * X - 4):(4 * X - 1) 12*4882a593Smuzhiyun * If the timer does not support PWM, bit 4 is reserved. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define AST_TMC_EN (1 << 0) 15*4882a593Smuzhiyun #define AST_TMC_1MHZ (1 << 1) 16*4882a593Smuzhiyun #define AST_TMC_OVFINTR (1 << 2) 17*4882a593Smuzhiyun #define AST_TMC_PWM (1 << 3) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Timers are counted from 1 in the datasheet. */ 20*4882a593Smuzhiyun #define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1)) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define AST_TMC_RATE (1000*1000) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * All timers share control registers, which makes it harder to make them 28*4882a593Smuzhiyun * separate devices. Since only one timer is needed at the moment, making 29*4882a593Smuzhiyun * it this just one device. 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct ast_timer_counter { 33*4882a593Smuzhiyun u32 status; 34*4882a593Smuzhiyun u32 reload_val; 35*4882a593Smuzhiyun u32 match1; 36*4882a593Smuzhiyun u32 match2; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct ast_timer { 40*4882a593Smuzhiyun struct ast_timer_counter timers1[3]; 41*4882a593Smuzhiyun u32 ctrl1; 42*4882a593Smuzhiyun u32 ctrl2; 43*4882a593Smuzhiyun #ifdef CONFIG_ASPEED_AST2500 44*4882a593Smuzhiyun u32 ctrl3; 45*4882a593Smuzhiyun u32 ctrl1_clr; 46*4882a593Smuzhiyun #else 47*4882a593Smuzhiyun u32 reserved[2]; 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun struct ast_timer_counter timers2[5]; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif /* _ASM_ARCH_TIMER_H */ 55