1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 Linaro 3*4882a593Smuzhiyun * Matt Waddel, <matt.waddel@linaro.org> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _SYSTIMER_H_ 8*4882a593Smuzhiyun #define _SYSTIMER_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* AMBA timer register base address */ 11*4882a593Smuzhiyun #define SYSTIMER_BASE 0x10011000 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */ 14*4882a593Smuzhiyun #define SYSTIMER_RELOAD 0xFFFFFFFF 15*4882a593Smuzhiyun #define SYSTIMER_EN (1 << 7) 16*4882a593Smuzhiyun #define SYSTIMER_32BIT (1 << 1) 17*4882a593Smuzhiyun #define SYSTIMER_PRESC_16 (1 << 2) 18*4882a593Smuzhiyun #define SYSTIMER_PRESC_256 (1 << 3) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct systimer { 21*4882a593Smuzhiyun u32 timer0load; /* 0x00 */ 22*4882a593Smuzhiyun u32 timer0value; 23*4882a593Smuzhiyun u32 timer0control; 24*4882a593Smuzhiyun u32 timer0intclr; 25*4882a593Smuzhiyun u32 timer0ris; 26*4882a593Smuzhiyun u32 timer0mis; 27*4882a593Smuzhiyun u32 timer0bgload; 28*4882a593Smuzhiyun u32 timer1load; /* 0x20 */ 29*4882a593Smuzhiyun u32 timer1value; 30*4882a593Smuzhiyun u32 timer1control; 31*4882a593Smuzhiyun u32 timer1intclr; 32*4882a593Smuzhiyun u32 timer1ris; 33*4882a593Smuzhiyun u32 timer1mis; 34*4882a593Smuzhiyun u32 timer1bgload; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun #endif /* _SYSTIMER_H_ */ 37