1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2012 3*4882a593Smuzhiyun * eInfochips Ltd. <www.einfochips.com> 4*4882a593Smuzhiyun * Written-by: Ajay Bhargav <contact@8051projects.net> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * (C) Copyright 2009 7*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __UTMI_ARMADA100__ 13*4882a593Smuzhiyun #define __UTMI_ARMADA100__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define UTMI_PHY_BASE 0xD4206000 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* utmi_ctrl - bits */ 18*4882a593Smuzhiyun #define INPKT_DELAY_SOF (1 << 28) 19*4882a593Smuzhiyun #define PLL_PWR_UP 2 20*4882a593Smuzhiyun #define PHY_PWR_UP 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* utmi_pll - bits */ 23*4882a593Smuzhiyun #define PLL_FBDIV_MASK 0x00000FF0 24*4882a593Smuzhiyun #define PLL_FBDIV 4 25*4882a593Smuzhiyun #define PLL_REFDIV_MASK 0x0000000F 26*4882a593Smuzhiyun #define PLL_REFDIV 0 27*4882a593Smuzhiyun #define PLL_READY 0x800000 28*4882a593Smuzhiyun #define VCOCAL_START (1 << 21) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define N_DIVIDER 0xEE 31*4882a593Smuzhiyun #define M_DIVIDER 0x0B 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* utmi_tx - bits */ 34*4882a593Smuzhiyun #define CK60_PHSEL 17 35*4882a593Smuzhiyun #define PHSEL_VAL 0x4 36*4882a593Smuzhiyun #define RCAL_START (1 << 12) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * USB PHY registers 40*4882a593Smuzhiyun * Refer Datasheet Appendix A.21 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun struct armd1usb_phy_reg { 43*4882a593Smuzhiyun u32 utmi_rev; /* USB PHY Revision */ 44*4882a593Smuzhiyun u32 utmi_ctrl; /* USB PHY Control register */ 45*4882a593Smuzhiyun u32 utmi_pll; /* PLL register */ 46*4882a593Smuzhiyun u32 utmi_tx; /* Tx register */ 47*4882a593Smuzhiyun u32 utmi_rx; /* Rx register */ 48*4882a593Smuzhiyun u32 utmi_ivref; /* IVREF register */ 49*4882a593Smuzhiyun u32 utmi_tst_g0; /* Test group 0 register */ 50*4882a593Smuzhiyun u32 utmi_tst_g1; /* Test group 1 register */ 51*4882a593Smuzhiyun u32 utmi_tst_g2; /* Test group 2 register */ 52*4882a593Smuzhiyun u32 utmi_tst_g3; /* Test group 3 register */ 53*4882a593Smuzhiyun u32 utmi_tst_g4; /* Test group 4 register */ 54*4882a593Smuzhiyun u32 utmi_tst_g5; /* Test group 5 register */ 55*4882a593Smuzhiyun u32 utmi_reserve; /* Reserve Register */ 56*4882a593Smuzhiyun u32 utmi_usb_int; /* USB interuppt register */ 57*4882a593Smuzhiyun u32 utmi_dbg_ctl; /* Debug control register */ 58*4882a593Smuzhiyun u32 utmi_otg_addon; /* OTG addon register */ 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun int utmi_init(void); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif /* __UTMI_ARMADA100__ */ 64