1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * eInfochips Ltd. <www.einfochips.com> 4*4882a593Smuzhiyun * Written-by: Ajay Bhargav <contact@8051projects.net> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * (C) Copyright 2010 7*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __ARMADA100_SPI_H_ 13*4882a593Smuzhiyun #define __ARMADA100_SPI_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <asm/arch/armada100.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE 18*4882a593Smuzhiyun #define SSP_REG_BASE(x) CAT_BASE_ADDR(x) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * SSP Serial Port Registers 22*4882a593Smuzhiyun * refer Appendix A.26 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun struct ssp_reg { 25*4882a593Smuzhiyun u32 sscr0; /* SSP Control Register 0 - 0x000 */ 26*4882a593Smuzhiyun u32 sscr1; /* SSP Control Register 1 - 0x004 */ 27*4882a593Smuzhiyun u32 sssr; /* SSP Status Register - 0x008 */ 28*4882a593Smuzhiyun u32 ssitr; /* SSP Interrupt Test Register - 0x00C */ 29*4882a593Smuzhiyun u32 ssdr; /* SSP Data Register - 0x010 */ 30*4882a593Smuzhiyun u32 pad1[5]; 31*4882a593Smuzhiyun u32 ssto; /* SSP Timeout Register - 0x028 */ 32*4882a593Smuzhiyun u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */ 33*4882a593Smuzhiyun u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */ 34*4882a593Smuzhiyun u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */ 35*4882a593Smuzhiyun u32 sstss; /* SSP Timeslot Status Register - 0x038 */ 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define DEFAULT_WORD_LEN 8 39*4882a593Smuzhiyun #define SSP_FLUSH_NUM 0x2000 40*4882a593Smuzhiyun #define RX_THRESH_DEF 8 41*4882a593Smuzhiyun #define TX_THRESH_DEF 8 42*4882a593Smuzhiyun #define TIMEOUT_DEF 1000 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ 45*4882a593Smuzhiyun #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ 46*4882a593Smuzhiyun #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ 47*4882a593Smuzhiyun #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity 48*4882a593Smuzhiyun setting */ 49*4882a593Smuzhiyun #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ 50*4882a593Smuzhiyun #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ 51*4882a593Smuzhiyun #define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ 52*4882a593Smuzhiyun #define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ 55*4882a593Smuzhiyun #define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ 56*4882a593Smuzhiyun #define SSCR1_TINTE (1 << 19) /* Receiver Time-out 57*4882a593Smuzhiyun Interrupt enable */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define SSCR0_DSS 0x0f /* Data Size Select (mask) */ 60*4882a593Smuzhiyun #define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */ 61*4882a593Smuzhiyun #define SSCR0_FRF 0x30 /* FRame Format (mask) */ 62*4882a593Smuzhiyun #define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial 63*4882a593Smuzhiyun Peripheral Interface */ 64*4882a593Smuzhiyun #define SSCR0_TI (0x1 << 4) /* TI's Synchronous 65*4882a593Smuzhiyun Serial Protocol (SSP) */ 66*4882a593Smuzhiyun #define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ 67*4882a593Smuzhiyun #define SSCR0_ECS (1 << 6) /* External clock select */ 68*4882a593Smuzhiyun #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port 69*4882a593Smuzhiyun Enable */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ 72*4882a593Smuzhiyun #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ 73*4882a593Smuzhiyun #define SSSR_BSY (1 << 4) /* SSP Busy */ 74*4882a593Smuzhiyun #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ 75*4882a593Smuzhiyun #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ 76*4882a593Smuzhiyun #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ 77*4882a593Smuzhiyun #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* __ARMADA100_SPI_H_ */ 80