1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * eInfochips Ltd. <www.einfochips.com> 4*4882a593Smuzhiyun * Written-by: Ajay Bhargav <contact@8051projects.net> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * (C) Copyright 2010 7*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _ASM_ARCH_GPIO_H 13*4882a593Smuzhiyun #define _ASM_ARCH_GPIO_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <asm/types.h> 16*4882a593Smuzhiyun #include <asm/arch/armada100.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define GPIO_HIGH 1 19*4882a593Smuzhiyun #define GPIO_LOW 0 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define GPIO_TO_REG(gp) (gp >> 5) 22*4882a593Smuzhiyun #define GPIO_TO_BIT(gp) (1 << (gp & 0x1F)) 23*4882a593Smuzhiyun #define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01) 24*4882a593Smuzhiyun get_gpio_base(int bank)25*4882a593Smuzhiyunstatic inline void *get_gpio_base(int bank) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun const unsigned int offset[4] = {0, 4, 8, 0x100}; 28*4882a593Smuzhiyun /* gpio register bank offset - refer Appendix A.36 */ 29*4882a593Smuzhiyun return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]); 30*4882a593Smuzhiyun } 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif /* _ASM_ARCH_GPIO_H */ 33