1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2006-2008 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author 6*4882a593Smuzhiyun * Mansoor Ahamed <mansoor.ahamed@ti.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Initial Code from: 9*4882a593Smuzhiyun * Richard Woodruff <r-woodruff2@ti.com> 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _MEM_H_ 15*4882a593Smuzhiyun #define _MEM_H_ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * GPMC settings - 19*4882a593Smuzhiyun * Definitions is as per the following format 20*4882a593Smuzhiyun * #define <PART>_GPMC_CONFIG<x> <value> 21*4882a593Smuzhiyun * Where: 22*4882a593Smuzhiyun * PART is the part name e.g. STNOR - Intel Strata Flash 23*4882a593Smuzhiyun * x is GPMC config registers from 1 to 6 (there will be 6 macros) 24*4882a593Smuzhiyun * Value is corresponding value 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * For every valid PRCM configuration there should be only one definition of 27*4882a593Smuzhiyun * the same. if values are independent of the board, this definition will be 28*4882a593Smuzhiyun * present in this file if values are dependent on the board, then this should 29*4882a593Smuzhiyun * go into corresponding mem-boardName.h file 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * Currently valid part Names are (PART): 32*4882a593Smuzhiyun * M_NAND - Micron NAND 33*4882a593Smuzhiyun * STNOR - STMicrolelctronics M29W128GL 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun #define GPMC_SIZE_256M 0x0 36*4882a593Smuzhiyun #define GPMC_SIZE_128M 0x8 37*4882a593Smuzhiyun #define GPMC_SIZE_64M 0xC 38*4882a593Smuzhiyun #define GPMC_SIZE_32M 0xE 39*4882a593Smuzhiyun #define GPMC_SIZE_16M 0xF 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define M_NAND_GPMC_CONFIG1 0x00000800 42*4882a593Smuzhiyun #define M_NAND_GPMC_CONFIG2 0x001e1e00 43*4882a593Smuzhiyun #define M_NAND_GPMC_CONFIG3 0x001e1e00 44*4882a593Smuzhiyun #define M_NAND_GPMC_CONFIG4 0x16051807 45*4882a593Smuzhiyun #define M_NAND_GPMC_CONFIG5 0x00151e1e 46*4882a593Smuzhiyun #define M_NAND_GPMC_CONFIG6 0x16000f80 47*4882a593Smuzhiyun #define M_NAND_GPMC_CONFIG7 0x00000008 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define STNOR_GPMC_CONFIG1 0x00001200 50*4882a593Smuzhiyun #define STNOR_GPMC_CONFIG2 0x00101000 51*4882a593Smuzhiyun #define STNOR_GPMC_CONFIG3 0x00030301 52*4882a593Smuzhiyun #define STNOR_GPMC_CONFIG4 0x10041004 53*4882a593Smuzhiyun #define STNOR_GPMC_CONFIG5 0x000C1010 54*4882a593Smuzhiyun #define STNOR_GPMC_CONFIG6 0x08070280 55*4882a593Smuzhiyun #define STNOR_GPMC_CONFIG7 0x00000F48 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* max number of GPMC Chip Selects */ 58*4882a593Smuzhiyun #define GPMC_MAX_CS 8 59*4882a593Smuzhiyun /* max number of GPMC regs */ 60*4882a593Smuzhiyun #define GPMC_MAX_REG 7 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define DBG_MPDB 6 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* endif _MEM_H_ */ 65