1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * clocks_am33xx.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * AM33xx clock define 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _CLOCKS_AM33XX_H_ 12*4882a593Smuzhiyun #define _CLOCKS_AM33XX_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* MAIN PLL Fdll supported frequencies */ 15*4882a593Smuzhiyun #define MPUPLL_M_1000 1000 16*4882a593Smuzhiyun #define MPUPLL_M_800 800 17*4882a593Smuzhiyun #define MPUPLL_M_720 720 18*4882a593Smuzhiyun #define MPUPLL_M_600 600 19*4882a593Smuzhiyun #define MPUPLL_M_500 500 20*4882a593Smuzhiyun #define MPUPLL_M_300 300 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define UART_RESET (0x1 << 1) 23*4882a593Smuzhiyun #define UART_CLK_RUNNING_MASK 0x1 24*4882a593Smuzhiyun #define UART_SMART_IDLE_EN (0x1 << 0x3) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CM_DLL_CTRL_NO_OVERRIDE 0x0 27*4882a593Smuzhiyun #define CM_DLL_READYST 0x4 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define NUM_OPPS 6 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun extern void enable_dmm_clocks(void); 32*4882a593Smuzhiyun extern void enable_emif_clocks(void); 33*4882a593Smuzhiyun extern const struct dpll_params dpll_core_opp100; 34*4882a593Smuzhiyun extern struct dpll_params dpll_mpu_opp100; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* endif _CLOCKS_AM33XX_H_ */ 37