1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * dts file for Xilinx ZynqMP ZCU102 RevB 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2016, Xilinx, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include "zynqmp-zcu102-revA.dts" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "ZynqMP ZCU102 RevB"; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun&gem3 { 18*4882a593Smuzhiyun phy-handle = <&phyc>; 19*4882a593Smuzhiyun phyc: phy@c { 20*4882a593Smuzhiyun reg = <0xc>; 21*4882a593Smuzhiyun ti,rx-internal-delay = <0x8>; 22*4882a593Smuzhiyun ti,tx-internal-delay = <0xa>; 23*4882a593Smuzhiyun ti,fifo-depth = <0x1>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun /* Cleanup from RevA */ 26*4882a593Smuzhiyun /delete-node/ phy@21; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun/* Different qspi 512Mbit version */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun/* Fix collision with u61 */ 32*4882a593Smuzhiyun&i2c0 { 33*4882a593Smuzhiyun i2cswitch@75 { 34*4882a593Smuzhiyun i2c@2 { 35*4882a593Smuzhiyun max15303@1b { /* u8 */ 36*4882a593Smuzhiyun compatible = "max15303"; 37*4882a593Smuzhiyun reg = <0x1b>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun /delete-node/ max15303@20; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43