1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Xilinx ZC706 board DTS 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011 - 2015 Xilinx 5*4882a593Smuzhiyun * Copyright (C) 2012 National Instruments Corp. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun#include "zynq-7000.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Zynq ZC706 Development Board"; 14*4882a593Smuzhiyun compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun aliases { 17*4882a593Smuzhiyun ethernet0 = &gem0; 18*4882a593Smuzhiyun i2c0 = &i2c0; 19*4882a593Smuzhiyun serial0 = &uart1; 20*4882a593Smuzhiyun spi0 = &qspi; 21*4882a593Smuzhiyun mmc0 = &sdhci0; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun memory@0 { 25*4882a593Smuzhiyun device_type = "memory"; 26*4882a593Smuzhiyun reg = <0x0 0x40000000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun chosen { 30*4882a593Smuzhiyun bootargs = ""; 31*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun usb_phy0: phy0 { 35*4882a593Smuzhiyun compatible = "usb-nop-xceiv"; 36*4882a593Smuzhiyun #phy-cells = <0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&clkc { 41*4882a593Smuzhiyun ps-clk-frequency = <33333333>; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&gem0 { 45*4882a593Smuzhiyun status = "okay"; 46*4882a593Smuzhiyun phy-mode = "rgmii-id"; 47*4882a593Smuzhiyun phy-handle = <ðernet_phy>; 48*4882a593Smuzhiyun pinctrl-names = "default"; 49*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gem0_default>; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun ethernet_phy: ethernet-phy@7 { 52*4882a593Smuzhiyun reg = <7>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun}; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun&gpio0 { 57*4882a593Smuzhiyun pinctrl-names = "default"; 58*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio0_default>; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&i2c0 { 62*4882a593Smuzhiyun status = "okay"; 63*4882a593Smuzhiyun clock-frequency = <400000>; 64*4882a593Smuzhiyun pinctrl-names = "default"; 65*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c0_default>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun i2cswitch@74 { 68*4882a593Smuzhiyun compatible = "nxp,pca9548"; 69*4882a593Smuzhiyun #address-cells = <1>; 70*4882a593Smuzhiyun #size-cells = <0>; 71*4882a593Smuzhiyun reg = <0x74>; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun i2c@0 { 74*4882a593Smuzhiyun #address-cells = <1>; 75*4882a593Smuzhiyun #size-cells = <0>; 76*4882a593Smuzhiyun reg = <0>; 77*4882a593Smuzhiyun si570: clock-generator@5d { 78*4882a593Smuzhiyun #clock-cells = <0>; 79*4882a593Smuzhiyun compatible = "silabs,si570"; 80*4882a593Smuzhiyun temperature-stability = <50>; 81*4882a593Smuzhiyun reg = <0x5d>; 82*4882a593Smuzhiyun factory-fout = <156250000>; 83*4882a593Smuzhiyun clock-frequency = <148500000>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun i2c@1 { 88*4882a593Smuzhiyun #address-cells = <1>; 89*4882a593Smuzhiyun #size-cells = <0>; 90*4882a593Smuzhiyun reg = <1>; 91*4882a593Smuzhiyun adv7511: hdmi-tx@39 { 92*4882a593Smuzhiyun compatible = "adi,adv7511"; 93*4882a593Smuzhiyun reg = <0x39>; 94*4882a593Smuzhiyun adi,input-depth = <8>; 95*4882a593Smuzhiyun adi,input-colorspace = "yuv422"; 96*4882a593Smuzhiyun adi,input-clock = "1x"; 97*4882a593Smuzhiyun adi,input-style = <3>; 98*4882a593Smuzhiyun adi,input-justification = "evenly"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun i2c@2 { 103*4882a593Smuzhiyun #address-cells = <1>; 104*4882a593Smuzhiyun #size-cells = <0>; 105*4882a593Smuzhiyun reg = <2>; 106*4882a593Smuzhiyun eeprom@54 { 107*4882a593Smuzhiyun compatible = "at,24c08"; 108*4882a593Smuzhiyun reg = <0x54>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun i2c@3 { 113*4882a593Smuzhiyun #address-cells = <1>; 114*4882a593Smuzhiyun #size-cells = <0>; 115*4882a593Smuzhiyun reg = <3>; 116*4882a593Smuzhiyun gpio@21 { 117*4882a593Smuzhiyun compatible = "ti,tca6416"; 118*4882a593Smuzhiyun reg = <0x21>; 119*4882a593Smuzhiyun gpio-controller; 120*4882a593Smuzhiyun #gpio-cells = <2>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun i2c@4 { 125*4882a593Smuzhiyun #address-cells = <1>; 126*4882a593Smuzhiyun #size-cells = <0>; 127*4882a593Smuzhiyun reg = <4>; 128*4882a593Smuzhiyun rtc@51 { 129*4882a593Smuzhiyun compatible = "nxp,pcf8563"; 130*4882a593Smuzhiyun reg = <0x51>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun i2c@7 { 135*4882a593Smuzhiyun #address-cells = <1>; 136*4882a593Smuzhiyun #size-cells = <0>; 137*4882a593Smuzhiyun reg = <7>; 138*4882a593Smuzhiyun ucd90120@65 { 139*4882a593Smuzhiyun compatible = "ti,ucd90120"; 140*4882a593Smuzhiyun reg = <0x65>; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun}; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun&pinctrl0 { 147*4882a593Smuzhiyun pinctrl_gem0_default: gem0-default { 148*4882a593Smuzhiyun mux { 149*4882a593Smuzhiyun function = "ethernet0"; 150*4882a593Smuzhiyun groups = "ethernet0_0_grp"; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun conf { 154*4882a593Smuzhiyun groups = "ethernet0_0_grp"; 155*4882a593Smuzhiyun slew-rate = <0>; 156*4882a593Smuzhiyun io-standard = <4>; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun conf-rx { 160*4882a593Smuzhiyun pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; 161*4882a593Smuzhiyun bias-high-impedance; 162*4882a593Smuzhiyun low-power-disable; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun conf-tx { 166*4882a593Smuzhiyun pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; 167*4882a593Smuzhiyun low-power-enable; 168*4882a593Smuzhiyun bias-disable; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun mux-mdio { 172*4882a593Smuzhiyun function = "mdio0"; 173*4882a593Smuzhiyun groups = "mdio0_0_grp"; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun conf-mdio { 177*4882a593Smuzhiyun groups = "mdio0_0_grp"; 178*4882a593Smuzhiyun slew-rate = <0>; 179*4882a593Smuzhiyun io-standard = <1>; 180*4882a593Smuzhiyun bias-disable; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun pinctrl_gpio0_default: gpio0-default { 185*4882a593Smuzhiyun mux { 186*4882a593Smuzhiyun function = "gpio0"; 187*4882a593Smuzhiyun groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun conf { 191*4882a593Smuzhiyun groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; 192*4882a593Smuzhiyun slew-rate = <0>; 193*4882a593Smuzhiyun io-standard = <1>; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun conf-pull-up { 197*4882a593Smuzhiyun pins = "MIO46", "MIO47"; 198*4882a593Smuzhiyun bias-pull-up; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun conf-pull-none { 202*4882a593Smuzhiyun pins = "MIO7"; 203*4882a593Smuzhiyun bias-disable; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun pinctrl_i2c0_default: i2c0-default { 208*4882a593Smuzhiyun mux { 209*4882a593Smuzhiyun groups = "i2c0_10_grp"; 210*4882a593Smuzhiyun function = "i2c0"; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun conf { 214*4882a593Smuzhiyun groups = "i2c0_10_grp"; 215*4882a593Smuzhiyun bias-pull-up; 216*4882a593Smuzhiyun slew-rate = <0>; 217*4882a593Smuzhiyun io-standard = <1>; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun pinctrl_sdhci0_default: sdhci0-default { 222*4882a593Smuzhiyun mux { 223*4882a593Smuzhiyun groups = "sdio0_2_grp"; 224*4882a593Smuzhiyun function = "sdio0"; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun conf { 228*4882a593Smuzhiyun groups = "sdio0_2_grp"; 229*4882a593Smuzhiyun slew-rate = <0>; 230*4882a593Smuzhiyun io-standard = <1>; 231*4882a593Smuzhiyun bias-disable; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun mux-cd { 235*4882a593Smuzhiyun groups = "gpio0_14_grp"; 236*4882a593Smuzhiyun function = "sdio0_cd"; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun conf-cd { 240*4882a593Smuzhiyun groups = "gpio0_14_grp"; 241*4882a593Smuzhiyun bias-high-impedance; 242*4882a593Smuzhiyun bias-pull-up; 243*4882a593Smuzhiyun slew-rate = <0>; 244*4882a593Smuzhiyun io-standard = <1>; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun mux-wp { 248*4882a593Smuzhiyun groups = "gpio0_15_grp"; 249*4882a593Smuzhiyun function = "sdio0_wp"; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun conf-wp { 253*4882a593Smuzhiyun groups = "gpio0_15_grp"; 254*4882a593Smuzhiyun bias-high-impedance; 255*4882a593Smuzhiyun bias-pull-up; 256*4882a593Smuzhiyun slew-rate = <0>; 257*4882a593Smuzhiyun io-standard = <1>; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun pinctrl_uart1_default: uart1-default { 262*4882a593Smuzhiyun mux { 263*4882a593Smuzhiyun groups = "uart1_10_grp"; 264*4882a593Smuzhiyun function = "uart1"; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun conf { 268*4882a593Smuzhiyun groups = "uart1_10_grp"; 269*4882a593Smuzhiyun slew-rate = <0>; 270*4882a593Smuzhiyun io-standard = <1>; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun conf-rx { 274*4882a593Smuzhiyun pins = "MIO49"; 275*4882a593Smuzhiyun bias-high-impedance; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun conf-tx { 279*4882a593Smuzhiyun pins = "MIO48"; 280*4882a593Smuzhiyun bias-disable; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun pinctrl_usb0_default: usb0-default { 285*4882a593Smuzhiyun mux { 286*4882a593Smuzhiyun groups = "usb0_0_grp"; 287*4882a593Smuzhiyun function = "usb0"; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun conf { 291*4882a593Smuzhiyun groups = "usb0_0_grp"; 292*4882a593Smuzhiyun slew-rate = <0>; 293*4882a593Smuzhiyun io-standard = <1>; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun conf-rx { 297*4882a593Smuzhiyun pins = "MIO29", "MIO31", "MIO36"; 298*4882a593Smuzhiyun bias-high-impedance; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun conf-tx { 302*4882a593Smuzhiyun pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", 303*4882a593Smuzhiyun "MIO35", "MIO37", "MIO38", "MIO39"; 304*4882a593Smuzhiyun bias-disable; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun}; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun&qspi { 310*4882a593Smuzhiyun u-boot,dm-pre-reloc; 311*4882a593Smuzhiyun status = "okay"; 312*4882a593Smuzhiyun}; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun&sdhci0 { 315*4882a593Smuzhiyun u-boot,dm-pre-reloc; 316*4882a593Smuzhiyun status = "okay"; 317*4882a593Smuzhiyun pinctrl-names = "default"; 318*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sdhci0_default>; 319*4882a593Smuzhiyun}; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun&uart1 { 322*4882a593Smuzhiyun u-boot,dm-pre-reloc; 323*4882a593Smuzhiyun status = "okay"; 324*4882a593Smuzhiyun pinctrl-names = "default"; 325*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1_default>; 326*4882a593Smuzhiyun}; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun&usb0 { 329*4882a593Smuzhiyun status = "okay"; 330*4882a593Smuzhiyun dr_mode = "host"; 331*4882a593Smuzhiyun usb-phy = <&usb_phy0>; 332*4882a593Smuzhiyun pinctrl-names = "default"; 333*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb0_default>; 334*4882a593Smuzhiyun}; 335