1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Xilinx ZC702 board DTS 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011 - 2015 Xilinx 5*4882a593Smuzhiyun * Copyright (C) 2012 National Instruments Corp. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun#include "zynq-7000.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Zynq ZC702 Development Board"; 14*4882a593Smuzhiyun compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun aliases { 17*4882a593Smuzhiyun ethernet0 = &gem0; 18*4882a593Smuzhiyun i2c0 = &i2c0; 19*4882a593Smuzhiyun serial0 = &uart1; 20*4882a593Smuzhiyun spi0 = &qspi; 21*4882a593Smuzhiyun mmc0 = &sdhci0; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun memory@0 { 25*4882a593Smuzhiyun device_type = "memory"; 26*4882a593Smuzhiyun reg = <0x0 0x40000000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun chosen { 30*4882a593Smuzhiyun bootargs = ""; 31*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun gpio-keys { 35*4882a593Smuzhiyun compatible = "gpio-keys"; 36*4882a593Smuzhiyun #address-cells = <1>; 37*4882a593Smuzhiyun #size-cells = <0>; 38*4882a593Smuzhiyun autorepeat; 39*4882a593Smuzhiyun sw14 { 40*4882a593Smuzhiyun label = "sw14"; 41*4882a593Smuzhiyun gpios = <&gpio0 12 0>; 42*4882a593Smuzhiyun linux,code = <108>; /* down */ 43*4882a593Smuzhiyun wakeup-source; 44*4882a593Smuzhiyun autorepeat; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun sw13 { 47*4882a593Smuzhiyun label = "sw13"; 48*4882a593Smuzhiyun gpios = <&gpio0 14 0>; 49*4882a593Smuzhiyun linux,code = <103>; /* up */ 50*4882a593Smuzhiyun wakeup-source; 51*4882a593Smuzhiyun autorepeat; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun leds { 56*4882a593Smuzhiyun compatible = "gpio-leds"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun ds23 { 59*4882a593Smuzhiyun label = "ds23"; 60*4882a593Smuzhiyun gpios = <&gpio0 10 0>; 61*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun usb_phy0: phy0 { 66*4882a593Smuzhiyun compatible = "usb-nop-xceiv"; 67*4882a593Smuzhiyun #phy-cells = <0>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&amba { 72*4882a593Smuzhiyun ocm: sram@fffc0000 { 73*4882a593Smuzhiyun compatible = "mmio-sram"; 74*4882a593Smuzhiyun reg = <0xfffc0000 0x10000>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun&can0 { 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun pinctrl-names = "default"; 81*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can0_default>; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&clkc { 85*4882a593Smuzhiyun ps-clk-frequency = <33333333>; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun&gem0 { 89*4882a593Smuzhiyun status = "okay"; 90*4882a593Smuzhiyun phy-mode = "rgmii-id"; 91*4882a593Smuzhiyun phy-handle = <ðernet_phy>; 92*4882a593Smuzhiyun pinctrl-names = "default"; 93*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gem0_default>; 94*4882a593Smuzhiyun phy-reset-gpio = <&gpio0 11 0>; 95*4882a593Smuzhiyun phy-reset-active-low; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun ethernet_phy: ethernet-phy@7 { 98*4882a593Smuzhiyun reg = <7>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&gpio0 { 103*4882a593Smuzhiyun pinctrl-names = "default"; 104*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio0_default>; 105*4882a593Smuzhiyun}; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun&i2c0 { 108*4882a593Smuzhiyun status = "okay"; 109*4882a593Smuzhiyun clock-frequency = <400000>; 110*4882a593Smuzhiyun pinctrl-names = "default"; 111*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c0_default>; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun i2cswitch@74 { 114*4882a593Smuzhiyun compatible = "nxp,pca9548"; 115*4882a593Smuzhiyun #address-cells = <1>; 116*4882a593Smuzhiyun #size-cells = <0>; 117*4882a593Smuzhiyun reg = <0x74>; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun i2c@0 { 120*4882a593Smuzhiyun #address-cells = <1>; 121*4882a593Smuzhiyun #size-cells = <0>; 122*4882a593Smuzhiyun reg = <0>; 123*4882a593Smuzhiyun si570: clock-generator@5d { 124*4882a593Smuzhiyun #clock-cells = <0>; 125*4882a593Smuzhiyun compatible = "silabs,si570"; 126*4882a593Smuzhiyun temperature-stability = <50>; 127*4882a593Smuzhiyun reg = <0x5d>; 128*4882a593Smuzhiyun factory-fout = <156250000>; 129*4882a593Smuzhiyun clock-frequency = <148500000>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun i2c@1 { 134*4882a593Smuzhiyun #address-cells = <1>; 135*4882a593Smuzhiyun #size-cells = <0>; 136*4882a593Smuzhiyun reg = <1>; 137*4882a593Smuzhiyun adv7511: hdmi-tx@39 { 138*4882a593Smuzhiyun compatible = "adi,adv7511"; 139*4882a593Smuzhiyun reg = <0x39>; 140*4882a593Smuzhiyun adi,input-depth = <8>; 141*4882a593Smuzhiyun adi,input-colorspace = "yuv422"; 142*4882a593Smuzhiyun adi,input-clock = "1x"; 143*4882a593Smuzhiyun adi,input-style = <3>; 144*4882a593Smuzhiyun adi,input-justification = "right"; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun i2c@2 { 149*4882a593Smuzhiyun #address-cells = <1>; 150*4882a593Smuzhiyun #size-cells = <0>; 151*4882a593Smuzhiyun reg = <2>; 152*4882a593Smuzhiyun eeprom@54 { 153*4882a593Smuzhiyun compatible = "at,24c08"; 154*4882a593Smuzhiyun reg = <0x54>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun i2c@3 { 159*4882a593Smuzhiyun #address-cells = <1>; 160*4882a593Smuzhiyun #size-cells = <0>; 161*4882a593Smuzhiyun reg = <3>; 162*4882a593Smuzhiyun gpio@21 { 163*4882a593Smuzhiyun compatible = "ti,tca6416"; 164*4882a593Smuzhiyun reg = <0x21>; 165*4882a593Smuzhiyun gpio-controller; 166*4882a593Smuzhiyun #gpio-cells = <2>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun i2c@4 { 171*4882a593Smuzhiyun #address-cells = <1>; 172*4882a593Smuzhiyun #size-cells = <0>; 173*4882a593Smuzhiyun reg = <4>; 174*4882a593Smuzhiyun rtc@51 { 175*4882a593Smuzhiyun compatible = "nxp,pcf8563"; 176*4882a593Smuzhiyun reg = <0x51>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun i2c@7 { 181*4882a593Smuzhiyun #address-cells = <1>; 182*4882a593Smuzhiyun #size-cells = <0>; 183*4882a593Smuzhiyun reg = <7>; 184*4882a593Smuzhiyun hwmon@52 { 185*4882a593Smuzhiyun compatible = "ti,ucd9248"; 186*4882a593Smuzhiyun reg = <52>; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun hwmon@53 { 189*4882a593Smuzhiyun compatible = "ti,ucd9248"; 190*4882a593Smuzhiyun reg = <53>; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun hwmon@54 { 193*4882a593Smuzhiyun compatible = "ti,ucd9248"; 194*4882a593Smuzhiyun reg = <54>; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&pinctrl0 { 201*4882a593Smuzhiyun pinctrl_can0_default: can0-default { 202*4882a593Smuzhiyun mux { 203*4882a593Smuzhiyun function = "can0"; 204*4882a593Smuzhiyun groups = "can0_9_grp"; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun conf { 208*4882a593Smuzhiyun groups = "can0_9_grp"; 209*4882a593Smuzhiyun slew-rate = <0>; 210*4882a593Smuzhiyun io-standard = <1>; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun conf-rx { 214*4882a593Smuzhiyun pins = "MIO46"; 215*4882a593Smuzhiyun bias-high-impedance; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun conf-tx { 219*4882a593Smuzhiyun pins = "MIO47"; 220*4882a593Smuzhiyun bias-disable; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun pinctrl_gem0_default: gem0-default { 225*4882a593Smuzhiyun mux { 226*4882a593Smuzhiyun function = "ethernet0"; 227*4882a593Smuzhiyun groups = "ethernet0_0_grp"; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun conf { 231*4882a593Smuzhiyun groups = "ethernet0_0_grp"; 232*4882a593Smuzhiyun slew-rate = <0>; 233*4882a593Smuzhiyun io-standard = <4>; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun conf-rx { 237*4882a593Smuzhiyun pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; 238*4882a593Smuzhiyun bias-high-impedance; 239*4882a593Smuzhiyun low-power-disable; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun conf-tx { 243*4882a593Smuzhiyun pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; 244*4882a593Smuzhiyun bias-disable; 245*4882a593Smuzhiyun low-power-enable; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun mux-mdio { 249*4882a593Smuzhiyun function = "mdio0"; 250*4882a593Smuzhiyun groups = "mdio0_0_grp"; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun conf-mdio { 254*4882a593Smuzhiyun groups = "mdio0_0_grp"; 255*4882a593Smuzhiyun slew-rate = <0>; 256*4882a593Smuzhiyun io-standard = <1>; 257*4882a593Smuzhiyun bias-disable; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun pinctrl_gpio0_default: gpio0-default { 262*4882a593Smuzhiyun mux { 263*4882a593Smuzhiyun function = "gpio0"; 264*4882a593Smuzhiyun groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", 265*4882a593Smuzhiyun "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", 266*4882a593Smuzhiyun "gpio0_13_grp", "gpio0_14_grp"; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun conf { 270*4882a593Smuzhiyun groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", 271*4882a593Smuzhiyun "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", 272*4882a593Smuzhiyun "gpio0_13_grp", "gpio0_14_grp"; 273*4882a593Smuzhiyun slew-rate = <0>; 274*4882a593Smuzhiyun io-standard = <1>; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun conf-pull-up { 278*4882a593Smuzhiyun pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; 279*4882a593Smuzhiyun bias-pull-up; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun conf-pull-none { 283*4882a593Smuzhiyun pins = "MIO7", "MIO8"; 284*4882a593Smuzhiyun bias-disable; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun pinctrl_i2c0_default: i2c0-default { 289*4882a593Smuzhiyun mux { 290*4882a593Smuzhiyun groups = "i2c0_10_grp"; 291*4882a593Smuzhiyun function = "i2c0"; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun conf { 295*4882a593Smuzhiyun groups = "i2c0_10_grp"; 296*4882a593Smuzhiyun bias-pull-up; 297*4882a593Smuzhiyun slew-rate = <0>; 298*4882a593Smuzhiyun io-standard = <1>; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun pinctrl_sdhci0_default: sdhci0-default { 303*4882a593Smuzhiyun mux { 304*4882a593Smuzhiyun groups = "sdio0_2_grp"; 305*4882a593Smuzhiyun function = "sdio0"; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun conf { 309*4882a593Smuzhiyun groups = "sdio0_2_grp"; 310*4882a593Smuzhiyun slew-rate = <0>; 311*4882a593Smuzhiyun io-standard = <1>; 312*4882a593Smuzhiyun bias-disable; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun mux-cd { 316*4882a593Smuzhiyun groups = "gpio0_0_grp"; 317*4882a593Smuzhiyun function = "sdio0_cd"; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun conf-cd { 321*4882a593Smuzhiyun groups = "gpio0_0_grp"; 322*4882a593Smuzhiyun bias-high-impedance; 323*4882a593Smuzhiyun bias-pull-up; 324*4882a593Smuzhiyun slew-rate = <0>; 325*4882a593Smuzhiyun io-standard = <1>; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun mux-wp { 329*4882a593Smuzhiyun groups = "gpio0_15_grp"; 330*4882a593Smuzhiyun function = "sdio0_wp"; 331*4882a593Smuzhiyun }; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun conf-wp { 334*4882a593Smuzhiyun groups = "gpio0_15_grp"; 335*4882a593Smuzhiyun bias-high-impedance; 336*4882a593Smuzhiyun bias-pull-up; 337*4882a593Smuzhiyun slew-rate = <0>; 338*4882a593Smuzhiyun io-standard = <1>; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun pinctrl_uart1_default: uart1-default { 343*4882a593Smuzhiyun mux { 344*4882a593Smuzhiyun groups = "uart1_10_grp"; 345*4882a593Smuzhiyun function = "uart1"; 346*4882a593Smuzhiyun }; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun conf { 349*4882a593Smuzhiyun groups = "uart1_10_grp"; 350*4882a593Smuzhiyun slew-rate = <0>; 351*4882a593Smuzhiyun io-standard = <1>; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun conf-rx { 355*4882a593Smuzhiyun pins = "MIO49"; 356*4882a593Smuzhiyun bias-high-impedance; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun conf-tx { 360*4882a593Smuzhiyun pins = "MIO48"; 361*4882a593Smuzhiyun bias-disable; 362*4882a593Smuzhiyun }; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun pinctrl_usb0_default: usb0-default { 366*4882a593Smuzhiyun mux { 367*4882a593Smuzhiyun groups = "usb0_0_grp"; 368*4882a593Smuzhiyun function = "usb0"; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun conf { 372*4882a593Smuzhiyun groups = "usb0_0_grp"; 373*4882a593Smuzhiyun slew-rate = <0>; 374*4882a593Smuzhiyun io-standard = <1>; 375*4882a593Smuzhiyun }; 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun conf-rx { 378*4882a593Smuzhiyun pins = "MIO29", "MIO31", "MIO36"; 379*4882a593Smuzhiyun bias-high-impedance; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun conf-tx { 383*4882a593Smuzhiyun pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", 384*4882a593Smuzhiyun "MIO35", "MIO37", "MIO38", "MIO39"; 385*4882a593Smuzhiyun bias-disable; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun }; 388*4882a593Smuzhiyun}; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun&qspi { 391*4882a593Smuzhiyun u-boot,dm-pre-reloc; 392*4882a593Smuzhiyun status = "okay"; 393*4882a593Smuzhiyun}; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun&sdhci0 { 396*4882a593Smuzhiyun u-boot,dm-pre-reloc; 397*4882a593Smuzhiyun status = "okay"; 398*4882a593Smuzhiyun pinctrl-names = "default"; 399*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sdhci0_default>; 400*4882a593Smuzhiyun}; 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun&uart1 { 403*4882a593Smuzhiyun u-boot,dm-pre-reloc; 404*4882a593Smuzhiyun status = "okay"; 405*4882a593Smuzhiyun pinctrl-names = "default"; 406*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1_default>; 407*4882a593Smuzhiyun}; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun&usb0 { 410*4882a593Smuzhiyun status = "okay"; 411*4882a593Smuzhiyun dr_mode = "host"; 412*4882a593Smuzhiyun usb-phy = <&usb_phy0>; 413*4882a593Smuzhiyun pinctrl-names = "default"; 414*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb0_default>; 415*4882a593Smuzhiyun}; 416