1*4882a593Smuzhiyun#include "tegra30.dtsi" 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/ { 4*4882a593Smuzhiyun model = "Avionic Design Tamonten NG"; 5*4882a593Smuzhiyun compatible = "ad,tamonten-ng", "nvidia,tegra30"; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun memory { 8*4882a593Smuzhiyun reg = <0x80000000 0x40000000>; 9*4882a593Smuzhiyun }; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun chosen { 12*4882a593Smuzhiyun stdout-path = &uartd; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun aliases { 16*4882a593Smuzhiyun i2c0 = "/i2c@7000c000"; 17*4882a593Smuzhiyun i2c1 = "/i2c@7000c700"; 18*4882a593Smuzhiyun i2c2 = "/i2c@7000c400"; 19*4882a593Smuzhiyun i2c3 = "/i2c@7000c500"; 20*4882a593Smuzhiyun i2c4 = "/i2c@7000d000"; 21*4882a593Smuzhiyun mmc0 = "/sdhci@78000600"; 22*4882a593Smuzhiyun mmc1 = "/sdhci@78000400"; 23*4882a593Smuzhiyun mmc2 = "/sdhci@78000000"; 24*4882a593Smuzhiyun usb0 = "/usb@7d008000"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* GEN1 */ 28*4882a593Smuzhiyun i2c@7000c000 { 29*4882a593Smuzhiyun status = "okay"; 30*4882a593Smuzhiyun clock-frequency = <100000>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* GEN2 */ 34*4882a593Smuzhiyun i2c@7000c400 { 35*4882a593Smuzhiyun clock-frequency = <100000>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* CAM */ 39*4882a593Smuzhiyun i2c@7000c500 { 40*4882a593Smuzhiyun status = "okay"; 41*4882a593Smuzhiyun clock-frequency = <100000>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* DDC */ 45*4882a593Smuzhiyun i2c@7000c700 { 46*4882a593Smuzhiyun status = "okay"; 47*4882a593Smuzhiyun clock-frequency = <100000>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* PWR */ 51*4882a593Smuzhiyun i2c@7000d000 { 52*4882a593Smuzhiyun status = "okay"; 53*4882a593Smuzhiyun clock-frequency = <100000>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* SD slot on the base board */ 57*4882a593Smuzhiyun sdhci@78000400 { 58*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 59*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; 60*4882a593Smuzhiyun bus-width = <4>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* EMMC on the COM module */ 64*4882a593Smuzhiyun sdhci@78000600 { 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun bus-width = <8>; 67*4882a593Smuzhiyun non-removable; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun usb@7d008000 { 71*4882a593Smuzhiyun status = "okay"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun clocks { 75*4882a593Smuzhiyun compatible = "simple-bus"; 76*4882a593Smuzhiyun #address-cells = <1>; 77*4882a593Smuzhiyun #size-cells = <0>; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun clk32k_in: clk@0 { 80*4882a593Smuzhiyun compatible = "fixed-clock"; 81*4882a593Smuzhiyun reg=<0>; 82*4882a593Smuzhiyun #clock-cells = <0>; 83*4882a593Smuzhiyun clock-frequency = <32768>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun}; 87