1*4882a593Smuzhiyun/dts-v1/; 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun#include "tegra124.dtsi" 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/ { 6*4882a593Smuzhiyun model = "NVIDIA Venice2"; 7*4882a593Smuzhiyun compatible = "nvidia,venice2", "nvidia,tegra124"; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun chosen { 10*4882a593Smuzhiyun stdout-path = &uarta; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun aliases { 14*4882a593Smuzhiyun i2c0 = "/i2c@7000d000"; 15*4882a593Smuzhiyun i2c1 = "/i2c@7000c000"; 16*4882a593Smuzhiyun i2c2 = "/i2c@7000c400"; 17*4882a593Smuzhiyun i2c3 = "/i2c@7000c500"; 18*4882a593Smuzhiyun i2c4 = "/i2c@7000c700"; 19*4882a593Smuzhiyun i2c5 = "/i2c@7000d100"; 20*4882a593Smuzhiyun mmc0 = "/sdhci@700b0600"; 21*4882a593Smuzhiyun mmc1 = "/sdhci@700b0400"; 22*4882a593Smuzhiyun spi0 = "/spi@7000d400"; 23*4882a593Smuzhiyun spi1 = "/spi@7000da00"; 24*4882a593Smuzhiyun usb0 = "/usb@7d000000"; 25*4882a593Smuzhiyun usb1 = "/usb@7d008000"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun memory { 29*4882a593Smuzhiyun device_type = "memory"; 30*4882a593Smuzhiyun reg = <0x80000000 0x80000000>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun i2c@7000c000 { 34*4882a593Smuzhiyun status = "okay"; 35*4882a593Smuzhiyun clock-frequency = <100000>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun i2c@7000c400 { 39*4882a593Smuzhiyun status = "okay"; 40*4882a593Smuzhiyun clock-frequency = <100000>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun i2c@7000c500 { 44*4882a593Smuzhiyun status = "okay"; 45*4882a593Smuzhiyun clock-frequency = <100000>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun i2c@7000c700 { 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun clock-frequency = <100000>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun i2c@7000d000 { 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun clock-frequency = <400000>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun i2c@7000d100 { 59*4882a593Smuzhiyun status = "okay"; 60*4882a593Smuzhiyun clock-frequency = <400000>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun spi@7000d400 { 64*4882a593Smuzhiyun status = "okay"; 65*4882a593Smuzhiyun spi-max-frequency = <25000000>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun spi@7000da00 { 69*4882a593Smuzhiyun status = "okay"; 70*4882a593Smuzhiyun spi-max-frequency = <25000000>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun sdhci@700b0400 { 74*4882a593Smuzhiyun status = "okay"; 75*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 76*4882a593Smuzhiyun power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 77*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; 78*4882a593Smuzhiyun bus-width = <4>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun sdhci@700b0600 { 82*4882a593Smuzhiyun status = "okay"; 83*4882a593Smuzhiyun bus-width = <8>; 84*4882a593Smuzhiyun non-removable; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun usb@7d000000 { 88*4882a593Smuzhiyun status = "okay"; 89*4882a593Smuzhiyun dr_mode = "otg"; 90*4882a593Smuzhiyun nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun usb@7d008000 { 94*4882a593Smuzhiyun status = "okay"; 95*4882a593Smuzhiyun nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun clocks { 99*4882a593Smuzhiyun compatible = "simple-bus"; 100*4882a593Smuzhiyun #address-cells = <1>; 101*4882a593Smuzhiyun #size-cells = <0>; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun clk32k_in: clock@0 { 104*4882a593Smuzhiyun compatible = "fixed-clock"; 105*4882a593Smuzhiyun reg = <0>; 106*4882a593Smuzhiyun #clock-cells = <0>; 107*4882a593Smuzhiyun clock-frequency = <32768>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun&uarta { 114*4882a593Smuzhiyun status = "okay"; 115*4882a593Smuzhiyun}; 116