1*4882a593Smuzhiyun/ { 2*4882a593Smuzhiyun aliases { 3*4882a593Smuzhiyun ethernet0 = &emac; 4*4882a593Smuzhiyun }; 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun soc { 7*4882a593Smuzhiyun emac: ethernet@01c30000 { 8*4882a593Smuzhiyun compatible = "allwinner,sun50i-a64-emac"; 9*4882a593Smuzhiyun reg = <0x01c30000 0x2000>, <0x01c00030 0x4>; 10*4882a593Smuzhiyun reg-names = "emac", "syscon"; 11*4882a593Smuzhiyun interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 12*4882a593Smuzhiyun resets = <&ccu RST_BUS_EMAC>; 13*4882a593Smuzhiyun reset-names = "ahb"; 14*4882a593Smuzhiyun clocks = <&ccu CLK_BUS_EMAC>; 15*4882a593Smuzhiyun clock-names = "ahb"; 16*4882a593Smuzhiyun #address-cells = <1>; 17*4882a593Smuzhiyun #size-cells = <0>; 18*4882a593Smuzhiyun pinctrl-names = "default"; 19*4882a593Smuzhiyun pinctrl-0 = <&rgmii_pins>; 20*4882a593Smuzhiyun phy-mode = "rgmii"; 21*4882a593Smuzhiyun phy = <&phy1>; 22*4882a593Smuzhiyun status = "okay"; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun phy1: ethernet-phy@1 { 25*4882a593Smuzhiyun reg = <1>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun&pio { 32*4882a593Smuzhiyun rmii_pins: rmii_pins { 33*4882a593Smuzhiyun allwinner,pins = "PD10", "PD11", "PD13", "PD14", 34*4882a593Smuzhiyun "PD17", "PD18", "PD19", "PD20", 35*4882a593Smuzhiyun "PD22", "PD23"; 36*4882a593Smuzhiyun allwinner,function = "emac"; 37*4882a593Smuzhiyun allwinner,drive = <3>; 38*4882a593Smuzhiyun allwinner,pull = <0>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun rgmii_pins: rgmii_pins { 42*4882a593Smuzhiyun allwinner,pins = "PD8", "PD9", "PD10", "PD11", 43*4882a593Smuzhiyun "PD12", "PD13", "PD15", 44*4882a593Smuzhiyun "PD16", "PD17", "PD18", "PD19", 45*4882a593Smuzhiyun "PD20", "PD21", "PD22", "PD23"; 46*4882a593Smuzhiyun allwinner,function = "emac"; 47*4882a593Smuzhiyun allwinner,drive = <3>; 48*4882a593Smuzhiyun allwinner,pull = <0>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun}; 51