1*4882a593Smuzhiyun/dts-v1/; 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/ { 4*4882a593Smuzhiyun model = "ST STV0991 application board"; 5*4882a593Smuzhiyun compatible = "st,stv0991"; 6*4882a593Smuzhiyun #address-cells = <1>; 7*4882a593Smuzhiyun #size-cells = <1>; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun chosen { 10*4882a593Smuzhiyun stdout-path = &uart0; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun memory { 14*4882a593Smuzhiyun device_type="memory"; 15*4882a593Smuzhiyun reg = <0x0 0x198000>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun uart0: serial@0x80406000 { 19*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 20*4882a593Smuzhiyun reg = <0x80406000 0x1000>; 21*4882a593Smuzhiyun clock = <2700000>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun aliases { 25*4882a593Smuzhiyun spi0 = "/spi@80203000"; /* QSPI */ 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun qspi: spi@80203000 { 29*4882a593Smuzhiyun compatible = "cadence,qspi"; 30*4882a593Smuzhiyun #address-cells = <1>; 31*4882a593Smuzhiyun #size-cells = <0>; 32*4882a593Smuzhiyun reg = <0x80203000 0x100>, 33*4882a593Smuzhiyun <0x40000000 0x1000000>; 34*4882a593Smuzhiyun clocks = <3750000>; 35*4882a593Smuzhiyun sram-size = <256>; 36*4882a593Smuzhiyun status = "okay"; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun flash0: n25q32@0 { 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <1>; 41*4882a593Smuzhiyun compatible = "spi-flash"; 42*4882a593Smuzhiyun reg = <0>; /* chip select */ 43*4882a593Smuzhiyun spi-max-frequency = <50000000>; 44*4882a593Smuzhiyun m25p,fast-read; 45*4882a593Smuzhiyun page-size = <256>; 46*4882a593Smuzhiyun block-size = <16>; /* 2^16, 64KB */ 47*4882a593Smuzhiyun tshsl-ns = <50>; 48*4882a593Smuzhiyun tsd2d-ns = <50>; 49*4882a593Smuzhiyun tchsh-ns = <4>; 50*4882a593Smuzhiyun tslch-ns = <4>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun}; 54