1*4882a593Smuzhiyun #ifndef _ST_PINCFG_H_ 2*4882a593Smuzhiyun #define _ST_PINCFG_H_ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* Alternate functions */ 5*4882a593Smuzhiyun #define ALT1 1 6*4882a593Smuzhiyun #define ALT2 2 7*4882a593Smuzhiyun #define ALT3 3 8*4882a593Smuzhiyun #define ALT4 4 9*4882a593Smuzhiyun #define ALT5 5 10*4882a593Smuzhiyun #define ALT6 6 11*4882a593Smuzhiyun #define ALT7 7 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Output enable */ 14*4882a593Smuzhiyun #define OE (1 << 27) 15*4882a593Smuzhiyun /* Pull Up */ 16*4882a593Smuzhiyun #define PU (1 << 26) 17*4882a593Smuzhiyun /* Open Drain */ 18*4882a593Smuzhiyun #define OD (1 << 25) 19*4882a593Smuzhiyun #define RT (1 << 23) 20*4882a593Smuzhiyun #define INVERTCLK (1 << 22) 21*4882a593Smuzhiyun #define CLKNOTDATA (1 << 21) 22*4882a593Smuzhiyun #define DOUBLE_EDGE (1 << 20) 23*4882a593Smuzhiyun #define CLK_A (0 << 18) 24*4882a593Smuzhiyun #define CLK_B (1 << 18) 25*4882a593Smuzhiyun #define CLK_C (2 << 18) 26*4882a593Smuzhiyun #define CLK_D (3 << 18) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* User-frendly defines for Pin Direction */ 29*4882a593Smuzhiyun /* oe = 0, pu = 0, od = 0 */ 30*4882a593Smuzhiyun #define IN (0) 31*4882a593Smuzhiyun /* oe = 0, pu = 1, od = 0 */ 32*4882a593Smuzhiyun #define IN_PU (PU) 33*4882a593Smuzhiyun /* oe = 1, pu = 0, od = 0 */ 34*4882a593Smuzhiyun #define OUT (OE) 35*4882a593Smuzhiyun /* oe = 1, pu = 0, od = 1 */ 36*4882a593Smuzhiyun #define BIDIR (OE | OD) 37*4882a593Smuzhiyun /* oe = 1, pu = 1, od = 1 */ 38*4882a593Smuzhiyun #define BIDIR_PU (OE | PU | OD) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* RETIME_TYPE */ 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * B Mode 43*4882a593Smuzhiyun * Bypass retime with optional delay parameter 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun #define BYPASS (0) 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * R0, R1, R0D, R1D modes 48*4882a593Smuzhiyun * single-edge data non inverted clock, retime data with clk 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun #define SE_NICLK_IO (RT) 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * RIV0, RIV1, RIV0D, RIV1D modes 53*4882a593Smuzhiyun * single-edge data inverted clock, retime data with clk 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun #define SE_ICLK_IO (RT | INVERTCLK) 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * R0E, R1E, R0ED, R1ED modes 58*4882a593Smuzhiyun * double-edge data, retime data with clk 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define DE_IO (RT | DOUBLE_EDGE) 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * CIV0, CIV1 modes with inverted clock 63*4882a593Smuzhiyun * Retiming the clk pins will park clock & reduce the noise within the core. 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun #define ICLK (RT | CLKNOTDATA | INVERTCLK) 66*4882a593Smuzhiyun /* 67*4882a593Smuzhiyun * CLK0, CLK1 modes with non-inverted clock 68*4882a593Smuzhiyun * Retiming the clk pins will park clock & reduce the noise within the core. 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun #define NICLK (RT | CLKNOTDATA) 71*4882a593Smuzhiyun #endif /* _ST_PINCFG_H_ */ 72