xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/socfpga_cyclone5_sr1500.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (C) 2015 Stefan Roese <sr@denx.de>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "socfpga_cyclone5.dtsi"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	model = "SoCFPGA Cyclone V SR1500";
11*4882a593Smuzhiyun	compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga";
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	chosen {
14*4882a593Smuzhiyun		bootargs = "console=ttyS0,115200";
15*4882a593Smuzhiyun	};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	aliases {
18*4882a593Smuzhiyun		/*
19*4882a593Smuzhiyun		 * This allows the ethaddr uboot environment variable
20*4882a593Smuzhiyun		 * contents to be added to the gmac1 device tree blob.
21*4882a593Smuzhiyun		 */
22*4882a593Smuzhiyun		ethernet0 = &gmac1;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	memory@0 {
26*4882a593Smuzhiyun		name = "memory";
27*4882a593Smuzhiyun		device_type = "memory";
28*4882a593Smuzhiyun		reg = <0x0 0x40000000>; /* 1GB */
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	soc {
32*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun&gmac1 {
37*4882a593Smuzhiyun	status = "okay";
38*4882a593Smuzhiyun	phy-mode = "rgmii";
39*4882a593Smuzhiyun};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun&gpio0 {
42*4882a593Smuzhiyun	status = "okay";
43*4882a593Smuzhiyun};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun&gpio1 {
46*4882a593Smuzhiyun	status = "okay";
47*4882a593Smuzhiyun};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun&gpio2 {
50*4882a593Smuzhiyun	status = "okay";
51*4882a593Smuzhiyun};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun&i2c0 {
54*4882a593Smuzhiyun	status = "okay";
55*4882a593Smuzhiyun	speed-mode = <0>;
56*4882a593Smuzhiyun};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun&i2c1 {
59*4882a593Smuzhiyun	status = "okay";
60*4882a593Smuzhiyun	speed-mode = <0>;
61*4882a593Smuzhiyun};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun&mmc0 {
64*4882a593Smuzhiyun	status = "okay";
65*4882a593Smuzhiyun	bus-width = <8>;
66*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
67*4882a593Smuzhiyun};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun&uart0 {
70*4882a593Smuzhiyun	status = "okay";
71*4882a593Smuzhiyun};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun&usb1 {
74*4882a593Smuzhiyun	status = "okay";
75*4882a593Smuzhiyun};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun&watchdog0 {
78*4882a593Smuzhiyun	status = "okay";
79*4882a593Smuzhiyun};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun&qspi {
82*4882a593Smuzhiyun	status = "okay";
83*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	flash0: n25q00@0 {
86*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
87*4882a593Smuzhiyun		#address-cells = <1>;
88*4882a593Smuzhiyun		#size-cells = <1>;
89*4882a593Smuzhiyun		compatible = "n25q00", "spi-flash";
90*4882a593Smuzhiyun		reg = <0>;      /* chip select */
91*4882a593Smuzhiyun		spi-max-frequency = <100000000>;
92*4882a593Smuzhiyun		m25p,fast-read;
93*4882a593Smuzhiyun		page-size = <256>;
94*4882a593Smuzhiyun		block-size = <16>; /* 2^16, 64KB */
95*4882a593Smuzhiyun		read-delay = <4>;  /* delay value in read data capture register */
96*4882a593Smuzhiyun		tshsl-ns = <50>;
97*4882a593Smuzhiyun		tsd2d-ns = <50>;
98*4882a593Smuzhiyun		tchsh-ns = <4>;
99*4882a593Smuzhiyun		tslch-ns = <4>;
100*4882a593Smuzhiyun	};
101*4882a593Smuzhiyun};
102