1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2012 Altera Corporation <www.altera.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun/* First 4KB has trampoline code for secondary cores. */ 9*4882a593Smuzhiyun/memreserve/ 0x00000000 0x0001000; 10*4882a593Smuzhiyun#include "socfpga.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun soc { 14*4882a593Smuzhiyun clkmgr@ffd04000 { 15*4882a593Smuzhiyun clocks { 16*4882a593Smuzhiyun osc1 { 17*4882a593Smuzhiyun clock-frequency = <25000000>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun mmc0: dwmmc0@ff704000 { 23*4882a593Smuzhiyun num-slots = <1>; 24*4882a593Smuzhiyun broken-cd; 25*4882a593Smuzhiyun bus-width = <4>; 26*4882a593Smuzhiyun cap-mmc-highspeed; 27*4882a593Smuzhiyun cap-sd-highspeed; 28*4882a593Smuzhiyun drvsel = <3>; 29*4882a593Smuzhiyun smplsel = <0>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun sysmgr@ffd08000 { 33*4882a593Smuzhiyun cpu1-start-addr = <0xffd080c4>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun}; 37