1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with 3*4882a593Smuzhiyun * UART support 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Licensed under GPLv2. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h> 11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 12*4882a593Smuzhiyun#include <dt-bindings/clock/at91.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun aliases { 16*4882a593Smuzhiyun serial5 = &uart0; 17*4882a593Smuzhiyun serial6 = &uart1; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun ahb { 21*4882a593Smuzhiyun apb { 22*4882a593Smuzhiyun pinctrl@fffff200 { 23*4882a593Smuzhiyun uart0 { 24*4882a593Smuzhiyun pinctrl_uart0: uart0-0 { 25*4882a593Smuzhiyun atmel,pins = 26*4882a593Smuzhiyun <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ 27*4882a593Smuzhiyun AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun uart1 { 32*4882a593Smuzhiyun pinctrl_uart1: uart1-0 { 33*4882a593Smuzhiyun atmel,pins = 34*4882a593Smuzhiyun <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ 35*4882a593Smuzhiyun AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun pmc: pmc@fffffc00 { 41*4882a593Smuzhiyun periphck { 42*4882a593Smuzhiyun uart0_clk: uart0_clk@16 { 43*4882a593Smuzhiyun #clock-cells = <0>; 44*4882a593Smuzhiyun reg = <16>; 45*4882a593Smuzhiyun atmel,clk-output-range = <0 66000000>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun uart1_clk: uart1_clk@17 { 49*4882a593Smuzhiyun #clock-cells = <0>; 50*4882a593Smuzhiyun reg = <17>; 51*4882a593Smuzhiyun atmel,clk-output-range = <0 66000000>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun uart0: serial@f0024000 { 57*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 58*4882a593Smuzhiyun reg = <0xf0024000 0x200>; 59*4882a593Smuzhiyun interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 60*4882a593Smuzhiyun pinctrl-names = "default"; 61*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart0>; 62*4882a593Smuzhiyun clocks = <&uart0_clk>; 63*4882a593Smuzhiyun clock-names = "usart"; 64*4882a593Smuzhiyun status = "disabled"; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun uart1: serial@f8028000 { 68*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 69*4882a593Smuzhiyun reg = <0xf8028000 0x200>; 70*4882a593Smuzhiyun interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; 71*4882a593Smuzhiyun pinctrl-names = "default"; 72*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 73*4882a593Smuzhiyun clocks = <&uart1_clk>; 74*4882a593Smuzhiyun clock-names = "usart"; 75*4882a593Smuzhiyun status = "disabled"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun}; 80