1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with 3*4882a593Smuzhiyun * 3 MMC ports 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Licensed under GPLv2. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h> 11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 12*4882a593Smuzhiyun#include <dt-bindings/clock/at91.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun ahb { 16*4882a593Smuzhiyun apb { 17*4882a593Smuzhiyun pinctrl@fffff200 { 18*4882a593Smuzhiyun mmc2 { 19*4882a593Smuzhiyun pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { 20*4882a593Smuzhiyun atmel,pins = 21*4882a593Smuzhiyun <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */ 22*4882a593Smuzhiyun AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */ 23*4882a593Smuzhiyun AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */ 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun pinctrl_mmc2_dat1_3: mmc2_dat1_3 { 26*4882a593Smuzhiyun atmel,pins = 27*4882a593Smuzhiyun <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ 28*4882a593Smuzhiyun AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ 29*4882a593Smuzhiyun AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun pmc: pmc@fffffc00 { 35*4882a593Smuzhiyun periphck { 36*4882a593Smuzhiyun mci2_clk: mci2_clk@23 { 37*4882a593Smuzhiyun #clock-cells = <0>; 38*4882a593Smuzhiyun reg = <23>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun mmc2: mmc@f8004000 { 44*4882a593Smuzhiyun compatible = "atmel,hsmci"; 45*4882a593Smuzhiyun reg = <0xf8004000 0x600>; 46*4882a593Smuzhiyun interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; 47*4882a593Smuzhiyun dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; 48*4882a593Smuzhiyun dma-names = "rxtx"; 49*4882a593Smuzhiyun pinctrl-names = "default"; 50*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; 51*4882a593Smuzhiyun clocks = <&mci2_clk>; 52*4882a593Smuzhiyun clock-names = "mci_clk"; 53*4882a593Smuzhiyun status = "disabled"; 54*4882a593Smuzhiyun #address-cells = <1>; 55*4882a593Smuzhiyun #size-cells = <0>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun}; 60