1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rv1108.dtsi" 10*4882a593Smuzhiyun#include "rv1108-u-boot.dtsi" 11*4882a593Smuzhiyun#include "rv1108-sdram-ddr3-400.dtsi" 12*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "Rockchip RV1108 Evaluation board"; 16*4882a593Smuzhiyun compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun memory@60000000 { 19*4882a593Smuzhiyun device_type = "memory"; 20*4882a593Smuzhiyun reg = <0x60000000 0x08000000>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun chosen { 24*4882a593Smuzhiyun stdout-path = "serial2:1500000n8"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun adc-keys { 28*4882a593Smuzhiyun compatible = "adc-keys"; 29*4882a593Smuzhiyun io-channels = <&saradc 0>; 30*4882a593Smuzhiyun volup-key { 31*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 32*4882a593Smuzhiyun label = "volume up"; 33*4882a593Smuzhiyun press-threshold-microvolt = <18000>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun backlight: backlight { 38*4882a593Smuzhiyun compatible = "pwm-backlight"; 39*4882a593Smuzhiyun pwms = <&pwm0 0 25000 0>; 40*4882a593Smuzhiyun default-brightness-level = <200>; 41*4882a593Smuzhiyun brightness-levels = < 42*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 43*4882a593Smuzhiyun 8 9 10 11 12 13 14 15 44*4882a593Smuzhiyun 16 17 18 19 20 21 22 23 45*4882a593Smuzhiyun 24 25 26 27 28 29 30 31 46*4882a593Smuzhiyun 32 33 34 35 36 37 38 39 47*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 48*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 49*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 50*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 51*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 52*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 53*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 54*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 55*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 56*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 57*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 58*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 59*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 60*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 61*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 62*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 63*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 64*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 65*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 66*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 67*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 68*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 69*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 70*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 71*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 72*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 73*4882a593Smuzhiyun 248 249 250 251 252 253 254 255>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun vcc5v0_otg: vcc5v0-otg-drv { 77*4882a593Smuzhiyun compatible = "regulator-fixed"; 78*4882a593Smuzhiyun enable-active-high; 79*4882a593Smuzhiyun regulator-name = "vcc5v0_otg"; 80*4882a593Smuzhiyun gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 81*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 82*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun vcc_phy: vcc-phy-regulator { 86*4882a593Smuzhiyun compatible = "regulator-fixed"; 87*4882a593Smuzhiyun enable-active-high; 88*4882a593Smuzhiyun regulator-name = "vcc_phy"; 89*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 90*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 91*4882a593Smuzhiyun regulator-always-on; 92*4882a593Smuzhiyun regulator-boot-on; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun}; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun&display_subsystem { 97*4882a593Smuzhiyun status = "okay"; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&dsi { 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun panel: panel@0 { 104*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 105*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; 106*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 107*4882a593Smuzhiyun prepare-delay-ms = <20>; 108*4882a593Smuzhiyun reset-delay-ms = <20>; 109*4882a593Smuzhiyun init-delay-ms = <20>; 110*4882a593Smuzhiyun enable-delay-ms = <20>; 111*4882a593Smuzhiyun reg =<0>; 112*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 113*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 114*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 115*4882a593Smuzhiyun dsi,lanes = <4>; 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun panel-init-sequence = [ 119*4882a593Smuzhiyun 39 00 06 F0 55 AA 52 08 00 120*4882a593Smuzhiyun 39 00 05 B0 0F 0F 1E 14 121*4882a593Smuzhiyun 15 00 02 B2 00 122*4882a593Smuzhiyun 15 00 02 B6 03 123*4882a593Smuzhiyun 39 00 15 C0 03 00 06 07 08 09 00 00 00 00 02 00 0A 0B 0C 0D 00 00 00 00 124*4882a593Smuzhiyun 39 00 11 C1 08 24 24 01 18 24 9F 85 08 24 24 01 18 24 95 85 125*4882a593Smuzhiyun 39 00 19 C2 03 05 1B 24 13 31 01 05 1B 24 13 31 03 05 1B 38 00 11 02 05 1B 38 00 11 126*4882a593Smuzhiyun 39 00 19 C3 02 05 1B 24 13 11 03 05 1B 24 13 11 03 05 1B 38 00 11 02 05 1B 38 00 11 127*4882a593Smuzhiyun 39 00 06 F0 55 AA 52 08 01 128*4882a593Smuzhiyun 15 00 02 B5 1E 129*4882a593Smuzhiyun 15 00 02 B6 2D 130*4882a593Smuzhiyun 15 00 02 B7 04 131*4882a593Smuzhiyun 15 00 02 B8 05 132*4882a593Smuzhiyun 15 00 02 B9 04 133*4882a593Smuzhiyun 15 00 02 BA 14 134*4882a593Smuzhiyun 15 00 02 BB 2F 135*4882a593Smuzhiyun 15 00 02 BE 12 136*4882a593Smuzhiyun 39 00 04 C2 00 35 07 137*4882a593Smuzhiyun 39 00 06 F0 55 AA 52 08 02 138*4882a593Smuzhiyun 15 00 02 C9 13 139*4882a593Smuzhiyun 39 00 04 D4 02 04 2C 140*4882a593Smuzhiyun 39 00 24 E1 00 91 AE CB E6 54 FF 1e 33 43 55 4F 66 78 8B 55 9D AC C0 CF 55 E0 e8 F2 FB AA 03 0D 15 1F AA 27 2C 31 34 141*4882a593Smuzhiyun 39 00 24 E2 00 AD C6 E4 FD 55 11 2A 3B 49 55 54 6B 7C 8F 55 A1 AF C3 D1 55 E2 EA F3 FC AA 04 0E 15 20 AA 28 2D 32 35 142*4882a593Smuzhiyun 39 00 24 E3 55 05 1E 37 4B 55 5A 64 72 7F 55 8B A3 B8 D1 A5 E4 F6 0E 23 AA 39 42 4F 59 AA 64 70 7A 86 AA 90 96 9C 9F 143*4882a593Smuzhiyun 39 00 07 8F 5A 96 3C C3 A5 69 144*4882a593Smuzhiyun 15 00 02 89 00 145*4882a593Smuzhiyun 39 00 04 8C 55 49 53 146*4882a593Smuzhiyun 15 00 02 9A 5A 147*4882a593Smuzhiyun 39 00 05 FF A5 5A 13 86 148*4882a593Smuzhiyun 39 00 03 FE 01 54 149*4882a593Smuzhiyun 15 00 02 35 00 150*4882a593Smuzhiyun 15 96 02 11 00 151*4882a593Smuzhiyun 15 32 02 29 00 152*4882a593Smuzhiyun ]; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun display-timings { 155*4882a593Smuzhiyun native-mode = <&timing_e555hbm2>; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun timing_e555hbm2: timing0 { 158*4882a593Smuzhiyun clock-frequency = <62000000>; 159*4882a593Smuzhiyun hactive = <720>; 160*4882a593Smuzhiyun vactive = <1280>; 161*4882a593Smuzhiyun hsync-len = <4>; 162*4882a593Smuzhiyun hback-porch = <20>; 163*4882a593Smuzhiyun hfront-porch = <32>; 164*4882a593Smuzhiyun vsync-len = <4>; 165*4882a593Smuzhiyun vback-porch = <15>; 166*4882a593Smuzhiyun vfront-porch = <15>; 167*4882a593Smuzhiyun hsync-active = <0>; 168*4882a593Smuzhiyun vsync-active = <0>; 169*4882a593Smuzhiyun de-active = <0>; 170*4882a593Smuzhiyun pixelclk-active = <0>; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&gmac { 177*4882a593Smuzhiyun status = "okay"; 178*4882a593Smuzhiyun clock_in_out ="output"; 179*4882a593Smuzhiyun phy-supply = <&vcc_phy>; 180*4882a593Smuzhiyun snps,reset-active-low; 181*4882a593Smuzhiyun snps,reset-delays-us = <0 10000 1000000>; 182*4882a593Smuzhiyun snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; 183*4882a593Smuzhiyun}; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun&emmc { 186*4882a593Smuzhiyun bus-width = <8>; 187*4882a593Smuzhiyun cap-mmc-highspeed; 188*4882a593Smuzhiyun supports-emmc; 189*4882a593Smuzhiyun disable-wp; 190*4882a593Smuzhiyun non-removable; 191*4882a593Smuzhiyun num-slots = <1>; 192*4882a593Smuzhiyun status = "okay"; 193*4882a593Smuzhiyun}; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun&mipi_dphy { 196*4882a593Smuzhiyun status = "okay"; 197*4882a593Smuzhiyun}; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun&pwm0 { 200*4882a593Smuzhiyun status = "okay"; 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&route_dsi { 204*4882a593Smuzhiyun status = "okay"; 205*4882a593Smuzhiyun}; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun&saradc { 208*4882a593Smuzhiyun status = "okay"; 209*4882a593Smuzhiyun}; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun&sdmmc { 212*4882a593Smuzhiyun bus-width = <4>; 213*4882a593Smuzhiyun cap-mmc-highspeed; 214*4882a593Smuzhiyun cap-sd-highspeed; 215*4882a593Smuzhiyun disable-wp; 216*4882a593Smuzhiyun max-frequency = <150000000>; 217*4882a593Smuzhiyun pinctrl-names = "default"; 218*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 219*4882a593Smuzhiyun status = "okay"; 220*4882a593Smuzhiyun}; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun&sfc { 223*4882a593Smuzhiyun compatible = "rockchip,rksfc"; 224*4882a593Smuzhiyun status = "okay"; 225*4882a593Smuzhiyun}; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun&u2phy { 228*4882a593Smuzhiyun status = "okay"; 229*4882a593Smuzhiyun}; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun&u2phy_otg { 232*4882a593Smuzhiyun status = "okay"; 233*4882a593Smuzhiyun}; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun&u2phy_host { 236*4882a593Smuzhiyun status = "okay"; 237*4882a593Smuzhiyun}; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun&uart0 { 240*4882a593Smuzhiyun status = "okay"; 241*4882a593Smuzhiyun}; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun&uart1 { 244*4882a593Smuzhiyun status = "okay"; 245*4882a593Smuzhiyun}; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun&uart2 { 248*4882a593Smuzhiyun status = "okay"; 249*4882a593Smuzhiyun}; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun&usb20_otg { 252*4882a593Smuzhiyun vbus-supply = <&vcc5v0_otg>; 253*4882a593Smuzhiyun status = "okay"; 254*4882a593Smuzhiyun}; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun&usb_host_ehci { 257*4882a593Smuzhiyun status = "okay"; 258*4882a593Smuzhiyun}; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun&usb_host_ohci { 261*4882a593Smuzhiyun status = "okay"; 262*4882a593Smuzhiyun}; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun&vop { 265*4882a593Smuzhiyun status = "okay"; 266*4882a593Smuzhiyun}; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun&i2c0 { 269*4882a593Smuzhiyun i2c-scl-rising-time-ns = <275>; 270*4882a593Smuzhiyun i2c-scl-falling-time-ns = <16>; 271*4882a593Smuzhiyun clock-frequency = <200000>; 272*4882a593Smuzhiyun nack-retry = <1>; 273*4882a593Smuzhiyun status = "okay"; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun rk805: pmic@18 { 276*4882a593Smuzhiyun compatible = "rockchip,rk805"; 277*4882a593Smuzhiyun status = "okay"; 278*4882a593Smuzhiyun reg = <0x18>; 279*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 280*4882a593Smuzhiyun interrupts = <6 IRQ_TYPE_LEVEL_LOW>; 281*4882a593Smuzhiyun pinctrl-names = "default"; 282*4882a593Smuzhiyun pinctrl-0 = <&pmic_int_l>; 283*4882a593Smuzhiyun rockchip,system-power-controller; 284*4882a593Smuzhiyun wakeup-source; 285*4882a593Smuzhiyun gpio-controller; 286*4882a593Smuzhiyun #gpio-cells = <2>; 287*4882a593Smuzhiyun #clock-cells = <1>; 288*4882a593Smuzhiyun clock-output-names = "xin32k", "rk805-clkout2"; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun pwrkey { 291*4882a593Smuzhiyun status = "okay"; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun regulators { 295*4882a593Smuzhiyun vdd_arm: DCDC_REG1 { 296*4882a593Smuzhiyun regulator-name = "vdd_arm"; 297*4882a593Smuzhiyun regulator-min-microvolt = <712500>; 298*4882a593Smuzhiyun regulator-max-microvolt = <1450000>; 299*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 300*4882a593Smuzhiyun regulator-boot-on; 301*4882a593Smuzhiyun regulator-always-on; 302*4882a593Smuzhiyun regulator-state-mem { 303*4882a593Smuzhiyun regulator-on-in-suspend; 304*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun vdd_cam: DCDC_REG2 { 309*4882a593Smuzhiyun regulator-name = "vdd_cam"; 310*4882a593Smuzhiyun regulator-min-microvolt = <712500>; 311*4882a593Smuzhiyun regulator-max-microvolt = <2000000>; 312*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 313*4882a593Smuzhiyun regulator-boot-on; 314*4882a593Smuzhiyun regulator-always-on; 315*4882a593Smuzhiyun regulator-state-mem { 316*4882a593Smuzhiyun regulator-on-in-suspend; 317*4882a593Smuzhiyun regulator-suspend-microvolt = <2000000>; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 322*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 323*4882a593Smuzhiyun regulator-boot-on; 324*4882a593Smuzhiyun regulator-always-on; 325*4882a593Smuzhiyun regulator-state-mem { 326*4882a593Smuzhiyun regulator-on-in-suspend; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun vcc_io: DCDC_REG4 { 331*4882a593Smuzhiyun regulator-name = "vcc_io"; 332*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 333*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 334*4882a593Smuzhiyun regulator-boot-on; 335*4882a593Smuzhiyun regulator-always-on; 336*4882a593Smuzhiyun regulator-state-mem { 337*4882a593Smuzhiyun regulator-on-in-suspend; 338*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun vdd_10: LDO_REG1 { 343*4882a593Smuzhiyun regulator-name = "vdd_10"; 344*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 345*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 346*4882a593Smuzhiyun regulator-boot-on; 347*4882a593Smuzhiyun regulator-always-on; 348*4882a593Smuzhiyun regulator-state-mem { 349*4882a593Smuzhiyun regulator-on-in-suspend; 350*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun vcc_18emmc: LDO_REG2 { 355*4882a593Smuzhiyun regulator-name = "vcc_18emmc"; 356*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 357*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 358*4882a593Smuzhiyun regulator-boot-on; 359*4882a593Smuzhiyun regulator-always-on; 360*4882a593Smuzhiyun regulator-state-mem { 361*4882a593Smuzhiyun regulator-on-in-suspend; 362*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun vdd_10_pmu: LDO_REG3 { 367*4882a593Smuzhiyun regulator-name = "vdd_10_pmu"; 368*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 369*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 370*4882a593Smuzhiyun regulator-boot-on; 371*4882a593Smuzhiyun regulator-always-on; 372*4882a593Smuzhiyun regulator-state-mem { 373*4882a593Smuzhiyun regulator-on-in-suspend; 374*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 375*4882a593Smuzhiyun }; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun}; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun&pinctrl { 382*4882a593Smuzhiyun pmic { 383*4882a593Smuzhiyun pmic_int_l: pmic-int-l { 384*4882a593Smuzhiyun rockchip,pins = 385*4882a593Smuzhiyun <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun }; 388*4882a593Smuzhiyun}; 389