xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/rk3399-evb.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier:     GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
10*4882a593Smuzhiyun#include "rk3399.dtsi"
11*4882a593Smuzhiyun#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
12*4882a593Smuzhiyun#include "rk3399-u-boot.dtsi"
13*4882a593Smuzhiyun#include <linux/media-bus-format.h>
14*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun/ {
17*4882a593Smuzhiyun	model = "Rockchip RK3399 Evaluation Board";
18*4882a593Smuzhiyun	compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
19*4882a593Smuzhiyun		     "google,rk3399evb-rev2";
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	/* RK3399 evb board */
22*4882a593Smuzhiyun	rk_key0 {
23*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
24*4882a593Smuzhiyun		compatible = "rockchip,key";
25*4882a593Smuzhiyun		status = "okay";
26*4882a593Smuzhiyun		io-channels = <&saradc 1>;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		vol-up-key0 {
29*4882a593Smuzhiyun			u-boot,dm-pre-reloc;
30*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
31*4882a593Smuzhiyun			label = "volume up";
32*4882a593Smuzhiyun			rockchip,adc_value = <1>;
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	/* RK3399PRO evb board */
37*4882a593Smuzhiyun	rk_key1 {
38*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
39*4882a593Smuzhiyun		compatible = "rockchip,key";
40*4882a593Smuzhiyun		status = "okay";
41*4882a593Smuzhiyun		io-channels = <&saradc 2>;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		vol-up-key1 {
44*4882a593Smuzhiyun			u-boot,dm-pre-reloc;
45*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
46*4882a593Smuzhiyun			label = "volume up";
47*4882a593Smuzhiyun			rockchip,adc_value = <10>;
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	vdd_center: vdd-center {
52*4882a593Smuzhiyun		compatible = "pwm-regulator";
53*4882a593Smuzhiyun		pwms = <&pwm3 0 25000 1>;
54*4882a593Smuzhiyun		regulator-name = "vdd_center";
55*4882a593Smuzhiyun		regulator-min-microvolt = <800000>;
56*4882a593Smuzhiyun		regulator-max-microvolt = <1400000>;
57*4882a593Smuzhiyun		regulator-init-microvolt = <950000>;
58*4882a593Smuzhiyun		regulator-always-on;
59*4882a593Smuzhiyun		regulator-boot-on;
60*4882a593Smuzhiyun		status = "okay";
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	vccsys: vccsys {
64*4882a593Smuzhiyun		compatible = "regulator-fixed";
65*4882a593Smuzhiyun		regulator-name = "vccsys";
66*4882a593Smuzhiyun		regulator-boot-on;
67*4882a593Smuzhiyun		regulator-always-on;
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	vcc3v3_sys: vcc3v3-sys {
71*4882a593Smuzhiyun		compatible = "regulator-fixed";
72*4882a593Smuzhiyun		regulator-name = "vcc3v3_sys";
73*4882a593Smuzhiyun		regulator-always-on;
74*4882a593Smuzhiyun		regulator-boot-on;
75*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
76*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
77*4882a593Smuzhiyun	};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	vcc_phy: vcc-phy-regulator {
80*4882a593Smuzhiyun		compatible = "regulator-fixed";
81*4882a593Smuzhiyun		regulator-name = "vcc_phy";
82*4882a593Smuzhiyun		regulator-always-on;
83*4882a593Smuzhiyun		regulator-boot-on;
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host-en {
87*4882a593Smuzhiyun		compatible = "regulator-fixed";
88*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
89*4882a593Smuzhiyun		gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
90*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
91*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
92*4882a593Smuzhiyun		regulator-always-on;
93*4882a593Smuzhiyun		regulator-boot-on;
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun	vcc5v0_typec0: vcc5v0-typec0-en {
97*4882a593Smuzhiyun		compatible = "regulator-fixed";
98*4882a593Smuzhiyun		regulator-name = "vcc5v0_typec0";
99*4882a593Smuzhiyun		gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
100*4882a593Smuzhiyun	};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun	vcc5v0_typec1: vcc5v0-typec1-en {
103*4882a593Smuzhiyun		compatible = "regulator-fixed";
104*4882a593Smuzhiyun		regulator-name = "vcc5v0_typec1";
105*4882a593Smuzhiyun		gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	clkin_gmac: external-gmac-clock {
109*4882a593Smuzhiyun		compatible = "fixed-clock";
110*4882a593Smuzhiyun		clock-frequency = <125000000>;
111*4882a593Smuzhiyun		clock-output-names = "clkin_gmac";
112*4882a593Smuzhiyun		#clock-cells = <0>;
113*4882a593Smuzhiyun	};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun	backlight: backlight {
116*4882a593Smuzhiyun		compatible = "pwm-backlight";
117*4882a593Smuzhiyun		power-supply = <&vccsys>;
118*4882a593Smuzhiyun		enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
119*4882a593Smuzhiyun		brightness-levels = <
120*4882a593Smuzhiyun			  0   1   2   3   4   5   6   7
121*4882a593Smuzhiyun			  8   9  10  11  12  13  14  15
122*4882a593Smuzhiyun			 16  17  18  19  20  21  22  23
123*4882a593Smuzhiyun			 24  25  26  27  28  29  30  31
124*4882a593Smuzhiyun			 32  33  34  35  36  37  38  39
125*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
126*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
127*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
128*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
129*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
130*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
131*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
132*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
133*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
134*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
135*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
136*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
137*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
138*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
139*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
140*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
141*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
142*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
143*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
144*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
145*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
146*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
147*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
148*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
149*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
150*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
151*4882a593Smuzhiyun			248 249 250 251 252 253 254 255>;
152*4882a593Smuzhiyun		default-brightness-level = <200>;
153*4882a593Smuzhiyun		pwms = <&pwm0 0 25000 0>;
154*4882a593Smuzhiyun		pinctrl-names = "default";
155*4882a593Smuzhiyun		pinctrl-0 = <&pwm0_pin>;
156*4882a593Smuzhiyun		pwm-delay-us = <10000>;
157*4882a593Smuzhiyun		status = "disabled";
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys {
161*4882a593Smuzhiyun		compatible = "regulator-fixed";
162*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
163*4882a593Smuzhiyun		regulator-always-on;
164*4882a593Smuzhiyun		regulator-boot-on;
165*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
166*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
167*4882a593Smuzhiyun	};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun	vcc_lcd: vcc-lcd {
170*4882a593Smuzhiyun		compatible = "regulator-fixed";
171*4882a593Smuzhiyun		regulator-name = "vcc_lcd";
172*4882a593Smuzhiyun		gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
173*4882a593Smuzhiyun		startup-delay-us = <20000>;
174*4882a593Smuzhiyun		enable-active-high;
175*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
176*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
177*4882a593Smuzhiyun		regulator-boot-on;
178*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
179*4882a593Smuzhiyun	};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun	panel: panel {
182*4882a593Smuzhiyun		compatible = "simple-panel";
183*4882a593Smuzhiyun		backlight = <&backlight>;
184*4882a593Smuzhiyun		power-supply = <&vcc_lcd>;
185*4882a593Smuzhiyun		enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
186*4882a593Smuzhiyun		prepare-delay-ms = <20>;
187*4882a593Smuzhiyun		enable-delay-ms = <20>;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun		display-timings {
190*4882a593Smuzhiyun			native-mode = <&timing0>;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun			timing0: timing0 {
193*4882a593Smuzhiyun				clock-frequency = <200000000>;
194*4882a593Smuzhiyun				hactive = <1536>;
195*4882a593Smuzhiyun				vactive = <2048>;
196*4882a593Smuzhiyun				hfront-porch = <12>;
197*4882a593Smuzhiyun				hsync-len = <16>;
198*4882a593Smuzhiyun				hback-porch = <48>;
199*4882a593Smuzhiyun				vfront-porch = <8>;
200*4882a593Smuzhiyun				vsync-len = <4>;
201*4882a593Smuzhiyun				vback-porch = <8>;
202*4882a593Smuzhiyun				hsync-active = <0>;
203*4882a593Smuzhiyun				vsync-active = <0>;
204*4882a593Smuzhiyun				de-active = <0>;
205*4882a593Smuzhiyun				pixelclk-active = <0>;
206*4882a593Smuzhiyun			};
207*4882a593Smuzhiyun		};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun		ports {
210*4882a593Smuzhiyun			panel_in: endpoint {
211*4882a593Smuzhiyun				remote-endpoint = <&edp_out>;
212*4882a593Smuzhiyun			};
213*4882a593Smuzhiyun		};
214*4882a593Smuzhiyun	};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun&crypto {
219*4882a593Smuzhiyun	status = "okay";
220*4882a593Smuzhiyun};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun&uart2 {
223*4882a593Smuzhiyun	status = "okay";
224*4882a593Smuzhiyun};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun&emmc_phy {
227*4882a593Smuzhiyun	status = "okay";
228*4882a593Smuzhiyun};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun&pwm0 {
231*4882a593Smuzhiyun	status = "okay";
232*4882a593Smuzhiyun};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun&pwm2 {
235*4882a593Smuzhiyun	status = "okay";
236*4882a593Smuzhiyun};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun&pwm3 {
239*4882a593Smuzhiyun	status = "okay";
240*4882a593Smuzhiyun};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun&saradc {
243*4882a593Smuzhiyun	status = "okay";
244*4882a593Smuzhiyun};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun&sdmmc {
247*4882a593Smuzhiyun	bus-width = <4>;
248*4882a593Smuzhiyun	status = "okay";
249*4882a593Smuzhiyun};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun&sdhci {
252*4882a593Smuzhiyun	bus-width = <8>;
253*4882a593Smuzhiyun	mmc-hs400-1_8v;
254*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
255*4882a593Smuzhiyun	non-removable;
256*4882a593Smuzhiyun	status = "okay";
257*4882a593Smuzhiyun};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun&tcphy0 {
260*4882a593Smuzhiyun	status = "okay";
261*4882a593Smuzhiyun};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun&tcphy1 {
264*4882a593Smuzhiyun	status = "okay";
265*4882a593Smuzhiyun};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun&usb_host0_ehci {
268*4882a593Smuzhiyun	status = "okay";
269*4882a593Smuzhiyun};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun&usb_host0_ohci {
272*4882a593Smuzhiyun	status = "okay";
273*4882a593Smuzhiyun};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun&usbdrd3_0 {
276*4882a593Smuzhiyun	status = "okay";
277*4882a593Smuzhiyun};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun&usbdrd3_1 {
280*4882a593Smuzhiyun	status = "okay";
281*4882a593Smuzhiyun};
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun&usbdrd_dwc3_0 {
284*4882a593Smuzhiyun	status = "okay";
285*4882a593Smuzhiyun};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun&usbdrd_dwc3_1 {
288*4882a593Smuzhiyun	status = "okay";
289*4882a593Smuzhiyun};
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun&usb_host1_ehci {
292*4882a593Smuzhiyun	status = "okay";
293*4882a593Smuzhiyun};
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun&usb_host1_ohci {
296*4882a593Smuzhiyun	status = "okay";
297*4882a593Smuzhiyun};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun&i2c0 {
300*4882a593Smuzhiyun	status = "okay";
301*4882a593Smuzhiyun	clock-frequency = <400000>;
302*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <50>;
303*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <100>;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun	rk808: pmic@1b {
306*4882a593Smuzhiyun		compatible = "rockchip,rk808";
307*4882a593Smuzhiyun		clock-output-names = "xin32k", "wifibt_32kin";
308*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
309*4882a593Smuzhiyun		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
310*4882a593Smuzhiyun		pinctrl-names = "default";
311*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int_l>;
312*4882a593Smuzhiyun		reg = <0x1b>;
313*4882a593Smuzhiyun		rockchip,system-power-controller;
314*4882a593Smuzhiyun		#clock-cells = <1>;
315*4882a593Smuzhiyun		status = "okay";
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun		vcc12-supply = <&vcc3v3_sys>;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun		regulators {
320*4882a593Smuzhiyun			vcc33_lcd: SWITCH_REG2 {
321*4882a593Smuzhiyun				regulator-always-on;
322*4882a593Smuzhiyun				regulator-boot-on;
323*4882a593Smuzhiyun				regulator-name = "vcc33_lcd";
324*4882a593Smuzhiyun			};
325*4882a593Smuzhiyun		};
326*4882a593Smuzhiyun	};
327*4882a593Smuzhiyun};
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun&mipi_dsi {
330*4882a593Smuzhiyun	status = "disabled";
331*4882a593Smuzhiyun	rockchip,panel = <&panel>;
332*4882a593Smuzhiyun	display-timings {
333*4882a593Smuzhiyun		timing0 {
334*4882a593Smuzhiyun		bits-per-pixel = <24>;
335*4882a593Smuzhiyun		clock-frequency = <160000000>;
336*4882a593Smuzhiyun		hfront-porch = <120>;
337*4882a593Smuzhiyun		hsync-len = <20>;
338*4882a593Smuzhiyun		hback-porch = <21>;
339*4882a593Smuzhiyun		hactive = <1200>;
340*4882a593Smuzhiyun		vfront-porch = <21>;
341*4882a593Smuzhiyun		vsync-len = <3>;
342*4882a593Smuzhiyun		vback-porch = <18>;
343*4882a593Smuzhiyun		vactive = <1920>;
344*4882a593Smuzhiyun		hsync-active = <0>;
345*4882a593Smuzhiyun		vsync-active = <0>;
346*4882a593Smuzhiyun		de-active = <1>;
347*4882a593Smuzhiyun		pixelclk-active = <0>;
348*4882a593Smuzhiyun		};
349*4882a593Smuzhiyun	};
350*4882a593Smuzhiyun};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun&pinctrl {
353*4882a593Smuzhiyun	pmic {
354*4882a593Smuzhiyun		pmic_int_l: pmic-int-l {
355*4882a593Smuzhiyun			rockchip,pins =
356*4882a593Smuzhiyun				<1 21 RK_FUNC_GPIO &pcfg_pull_up>;
357*4882a593Smuzhiyun		};
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun		pmic_dvs2: pmic-dvs2 {
360*4882a593Smuzhiyun			rockchip,pins =
361*4882a593Smuzhiyun				<1 18 RK_FUNC_GPIO &pcfg_pull_down>;
362*4882a593Smuzhiyun		};
363*4882a593Smuzhiyun	};
364*4882a593Smuzhiyun};
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun&gmac {
367*4882a593Smuzhiyun        phy-supply = <&vcc_phy>;
368*4882a593Smuzhiyun	phy-mode = "rgmii";
369*4882a593Smuzhiyun	clock_in_out = "input";
370*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
371*4882a593Smuzhiyun	snps,reset-active-low;
372*4882a593Smuzhiyun	snps,reset-delays-us = <0 10000 50000>;
373*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_RMII_SRC>;
374*4882a593Smuzhiyun	assigned-clock-parents = <&clkin_gmac>;
375*4882a593Smuzhiyun	pinctrl-names = "default";
376*4882a593Smuzhiyun	pinctrl-0 = <&rgmii_pins>;
377*4882a593Smuzhiyun	tx_delay = <0x28>;
378*4882a593Smuzhiyun	rx_delay = <0x11>;
379*4882a593Smuzhiyun	status = "okay";
380*4882a593Smuzhiyun};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun&backlight {
383*4882a593Smuzhiyun	status = "okay";
384*4882a593Smuzhiyun	enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
385*4882a593Smuzhiyun};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun&route_edp {
388*4882a593Smuzhiyun	status = "okay";
389*4882a593Smuzhiyun};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun&edp_in_vopl {
392*4882a593Smuzhiyun	status = "disabled";
393*4882a593Smuzhiyun};
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun&edp_in_vopb {
396*4882a593Smuzhiyun	status = "okay";
397*4882a593Smuzhiyun};
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun&edp {
400*4882a593Smuzhiyun	status = "okay";
401*4882a593Smuzhiyun	force-hpd;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun	ports {
404*4882a593Smuzhiyun		port@1 {
405*4882a593Smuzhiyun			reg = <1>;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun			edp_out: endpoint {
408*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
409*4882a593Smuzhiyun			};
410*4882a593Smuzhiyun		};
411*4882a593Smuzhiyun	};
412*4882a593Smuzhiyun};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun&vopb {
415*4882a593Smuzhiyun	status = "okay";
416*4882a593Smuzhiyun};
417