1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ X11 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun config { 9*4882a593Smuzhiyun u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */ 10*4882a593Smuzhiyun u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun chosen { 14*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 15*4882a593Smuzhiyun u-boot,spl-boot-order = &emmc, &sdmmc; 16*4882a593Smuzhiyun tick-timer = "/timer@ff810000"; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun}; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun&pinctrl { 22*4882a593Smuzhiyun u-boot,dm-pre-reloc; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun&service_msch { 26*4882a593Smuzhiyun u-boot,dm-pre-reloc; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&dmc { 30*4882a593Smuzhiyun u-boot,dm-pre-reloc; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * Validation of throughput using SPEC2000 shows the following 34*4882a593Smuzhiyun * relative performance for the different memory schedules: 35*4882a593Smuzhiyun * - CBDR: 30.1 36*4882a593Smuzhiyun * - CBRD: 29.8 37*4882a593Smuzhiyun * - CRBD: 29.9 38*4882a593Smuzhiyun * Note that the best performance for any given application workload 39*4882a593Smuzhiyun * may vary from the default configured here (e.g. 164.gzip is fastest 40*4882a593Smuzhiyun * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD). 41*4882a593Smuzhiyun * 42*4882a593Smuzhiyun * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for 43*4882a593Smuzhiyun * details on the 'rockchip,memory-schedule' property and how it 44*4882a593Smuzhiyun * affects the physical-address to device-address mapping. 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun rockchip,memory-schedule = <DMC_MSCH_CBDR>; 47*4882a593Smuzhiyun rockchip,ddr-frequency = <800000000>; 48*4882a593Smuzhiyun rockchip,ddr-speed-bin = <DDR3_1600K>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun status = "okay"; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun&pmugrf { 54*4882a593Smuzhiyun u-boot,dm-pre-reloc; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&sgrf { 58*4882a593Smuzhiyun u-boot,dm-pre-reloc; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&cru { 62*4882a593Smuzhiyun u-boot,dm-pre-reloc; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&grf { 66*4882a593Smuzhiyun u-boot,dm-pre-reloc; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun&uart0 { 70*4882a593Smuzhiyun u-boot,dm-pre-reloc; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun&emmc { 74*4882a593Smuzhiyun u-boot,dm-spl; 75*4882a593Smuzhiyun}; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun&sdmmc { 78*4882a593Smuzhiyun u-boot,dm-spl; 79*4882a593Smuzhiyun}; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun&spi1 { 82*4882a593Smuzhiyun u-boot,dm-spl; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun spiflash: w25q32dw@0 { 85*4882a593Smuzhiyun u-boot,dm-spl; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun}; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun&timer0 { 90*4882a593Smuzhiyun u-boot,dm-pre-reloc; 91*4882a593Smuzhiyun clock-frequency = <24000000>; 92*4882a593Smuzhiyun status = "okay"; 93*4882a593Smuzhiyun}; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun 96