1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3328-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3328"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 mmc0 = &emmc; 29 mmc1 = &sdmmc; 30 mmc2 = &sdmmc_ext; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42// clocks = <&cru ARMCLK>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 }; 45 cpu1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0x0 0x1>; 49 enable-method = "psci"; 50 }; 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x2>; 55 enable-method = "psci"; 56 }; 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x3>; 61 enable-method = "psci"; 62 }; 63 }; 64 65 cpu0_opp_table: opp_table0 { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp@408000000 { 70 opp-hz = /bits/ 64 <408000000>; 71 opp-microvolt = <950000>; 72 clock-latency-ns = <40000>; 73 opp-suspend; 74 }; 75 opp@600000000 { 76 opp-hz = /bits/ 64 <600000000>; 77 opp-microvolt = <950000>; 78 clock-latency-ns = <40000>; 79 }; 80 opp@816000000 { 81 opp-hz = /bits/ 64 <816000000>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <40000>; 84 }; 85 opp@1008000000 { 86 opp-hz = /bits/ 64 <1008000000>; 87 opp-microvolt = <1100000>; 88 clock-latency-ns = <40000>; 89 }; 90 opp@1200000000 { 91 opp-hz = /bits/ 64 <1200000000>; 92 opp-microvolt = <1225000>; 93 clock-latency-ns = <40000>; 94 }; 95 opp@1296000000 { 96 opp-hz = /bits/ 64 <1296000000>; 97 opp-microvolt = <1300000>; 98 clock-latency-ns = <40000>; 99 }; 100 }; 101 102 arm-pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 109 }; 110 111 psci: psci { 112 compatible = "arm,psci-1.0"; 113 method = "smc"; 114 }; 115 116 timer { 117 compatible = "arm,armv8-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 122 }; 123 124 xin24m: xin24m { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <24000000>; 128 clock-output-names = "xin24m"; 129 }; 130 131 i2s0: i2s@ff000000 { 132 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 133 reg = <0x0 0xff000000 0x0 0x1000>; 134 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 136 clock-names = "i2s_clk", "i2s_hclk"; 137 dmas = <&dmac 11>, <&dmac 12>; 138 #dma-cells = <2>; 139 dma-names = "tx", "rx"; 140 status = "disabled"; 141 }; 142 143 i2s1: i2s@ff010000 { 144 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 145 reg = <0x0 0xff010000 0x0 0x1000>; 146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 148 clock-names = "i2s_clk", "i2s_hclk"; 149 dmas = <&dmac 14>, <&dmac 15>; 150 #dma-cells = <2>; 151 dma-names = "tx", "rx"; 152 status = "disabled"; 153 }; 154 155 i2s2: i2s@ff020000 { 156 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x0 0xff020000 0x0 0x1000>; 158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 160 clock-names = "i2s_clk", "i2s_hclk"; 161 dmas = <&dmac 0>, <&dmac 1>; 162 #dma-cells = <2>; 163 dma-names = "tx", "rx"; 164 pinctrl-names = "default", "sleep"; 165 pinctrl-0 = <&i2s2m0_mclk 166 &i2s2m0_sclk 167 &i2s2m0_lrcktx 168 &i2s2m0_lrckrx 169 &i2s2m0_sdo 170 &i2s2m0_sdi>; 171 pinctrl-1 = <&i2s2m0_sleep>; 172 status = "disabled"; 173 }; 174 175 spdif: spdif@ff030000 { 176 compatible = "rockchip,rk3328-spdif"; 177 reg = <0x0 0xff030000 0x0 0x1000>; 178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 180 clock-names = "mclk", "hclk"; 181 dmas = <&dmac 10>; 182 #dma-cells = <1>; 183 dma-names = "tx"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&spdifm2_tx>; 186 status = "disabled"; 187 }; 188 189 crypto: crypto@ff060000 { 190 compatible = "rockchip,rk322x-crypto"; 191 reg = <0x0 0xff060000 0x0 0x10000>; 192 clock-names = "sclk_crypto"; 193 clocks = <&cru SCLK_CRYPTO>; 194 status = "disabled"; 195 }; 196 197 grf: syscon@ff100000 { 198 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 199 reg = <0x0 0xff100000 0x0 0x1000>; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 203 io_domains: io-domains { 204 compatible = "rockchip,rk3328-io-voltage-domain"; 205 status = "disabled"; 206 }; 207 }; 208 209 uart0: serial@ff110000 { 210 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 211 reg = <0x0 0xff110000 0x0 0x100>; 212 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 214 clock-names = "baudclk", "apb_pclk"; 215 reg-shift = <2>; 216 reg-io-width = <4>; 217 dmas = <&dmac 2>, <&dmac 3>; 218 #dma-cells = <2>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 221 status = "disabled"; 222 }; 223 224 uart1: serial@ff120000 { 225 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 226 reg = <0x0 0xff120000 0x0 0x100>; 227 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 229 clock-names = "sclk_uart", "pclk_uart"; 230 reg-shift = <2>; 231 reg-io-width = <4>; 232 dmas = <&dmac 4>, <&dmac 5>; 233 #dma-cells = <2>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 236 status = "disabled"; 237 }; 238 239 uart2: serial@ff130000 { 240 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 241 reg = <0x0 0xff130000 0x0 0x100>; 242 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 244 clock-names = "baudclk", "apb_pclk"; 245 clock-frequency = <24000000>; 246 reg-shift = <2>; 247 reg-io-width = <4>; 248 dmas = <&dmac 6>, <&dmac 7>; 249 #dma-cells = <2>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&uart2m1_xfer>; 252 status = "disabled"; 253 }; 254 255 pmu: power-management@ff140000 { 256 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; 257 reg = <0x0 0xff140000 0x0 0x1000>; 258 }; 259 260 i2c0: i2c@ff150000 { 261 compatible = "rockchip,rk3328-i2c"; 262 reg = <0x0 0xff150000 0x0 0x1000>; 263 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 267 clock-names = "i2c", "pclk"; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&i2c0_xfer>; 270 status = "disabled"; 271 }; 272 273 i2c1: i2c@ff160000 { 274 compatible = "rockchip,rk3328-i2c"; 275 reg = <0x0 0xff160000 0x0 0x1000>; 276 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 280 clock-names = "i2c", "pclk"; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&i2c1_xfer>; 283 status = "disabled"; 284 }; 285 286 i2c2: i2c@ff170000 { 287 compatible = "rockchip,rk3328-i2c"; 288 reg = <0x0 0xff170000 0x0 0x1000>; 289 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 293 clock-names = "i2c", "pclk"; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&i2c2_xfer>; 296 status = "disabled"; 297 }; 298 299 i2c3: i2c@ff180000 { 300 compatible = "rockchip,rk3328-i2c"; 301 reg = <0x0 0xff180000 0x0 0x1000>; 302 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 306 clock-names = "i2c", "pclk"; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&i2c3_xfer>; 309 status = "disabled"; 310 }; 311 312 spi0: spi@ff190000 { 313 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 314 reg = <0x0 0xff190000 0x0 0x1000>; 315 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 319 clock-names = "spiclk", "apb_pclk"; 320 dmas = <&dmac 8>, <&dmac 9>; 321 #dma-cells = <2>; 322 dma-names = "tx", "rx"; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 325 status = "disabled"; 326 }; 327 328 wdt: watchdog@ff1a0000 { 329 compatible = "snps,dw-wdt"; 330 reg = <0x0 0xff1a0000 0x0 0x100>; 331 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 332 status = "disabled"; 333 }; 334 335 amba { 336 compatible = "simple-bus"; 337 #address-cells = <2>; 338 #size-cells = <2>; 339 ranges; 340 341 dmac: dmac@ff1f0000 { 342 compatible = "arm,pl330", "arm,primecell"; 343 reg = <0x0 0xff1f0000 0x0 0x4000>; 344 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&cru ACLK_DMAC>; 347 clock-names = "apb_pclk"; 348 #dma-cells = <1>; 349 }; 350 }; 351 352 saradc: saradc@ff280000 { 353 compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; 354 reg = <0x0 0xff280000 0x0 0x100>; 355 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 356 #io-channel-cells = <1>; 357 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 358 clock-names = "saradc", "apb_pclk"; 359 resets = <&cru SRST_SARADC_P>; 360 reset-names = "saradc-apb"; 361 status = "disabled"; 362 }; 363 364 dmc: dmc { 365 compatible = "rockchip,rk3328-dmc"; 366 reg = <0x0 0xff400000 0x0 0x1000 367 0x0 0xff780000 0x0 0x3000 368 0x0 0xff100000 0x0 0x1000 369 0x0 0xff440000 0x0 0x1000 370 0x0 0xff720000 0x0 0x1000 371 0x0 0xff798000 0x0 0x1000>; 372 }; 373 374 cru: clock-controller@ff440000 { 375 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 376 reg = <0x0 0xff440000 0x0 0x1000>; 377 rockchip,grf = <&grf>; 378 #clock-cells = <1>; 379 #reset-cells = <1>; 380 assigned-clocks = 381 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 382 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 383 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 384 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 385 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 386 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 387 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 388 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 389 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 390 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 391 <&cru SCLK_WIFI>, <&cru ARMCLK>, 392 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 393 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 394 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 395 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 396 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, 397 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, 398 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 399 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 400 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 401 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 402 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, 403 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 404 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; 405 assigned-clock-parents = 406 <&cru HDMIPHY>, <&cru PLL_APLL>, 407 <&cru PLL_GPLL>, <&xin24m>, 408 <&xin24m>, <&xin24m>; 409 assigned-clock-rates = 410 <0>, <61440000>, 411 <0>, <24000000>, 412 <24000000>, <24000000>, 413 <150000000>, <150000000>, 414 <100000000>, <100000000>, 415 <100000000>, <100000000>, 416 <50000000>, <100000000>, 417 <100000000>, <100000000>, 418 <50000000>, <50000000>, 419 <50000000>, <50000000>, 420 <24000000>, <600000000>, 421 <491520000>, <1200000000>, 422 <150000000>, <75000000>, 423 <75000000>, <150000000>, 424 <75000000>, <75000000>, 425 <300000000>, <100000000>, 426 <300000000>, <200000000>, 427 <400000000>, <500000000>, 428 <200000000>, <300000000>, 429 <300000000>, <250000000>, 430 <200000000>, <100000000>, 431 <24000000>, <100000000>, 432 <150000000>, <50000000>, 433 <32768>, <32768>; 434 }; 435 436 usb2phy_grf: syscon@ff450000 { 437 compatible = "rockchip,rk3328-usb2phy-grf", 438 "simple-mfd", "syscon"; 439 reg = <0x0 0xff450000 0x0 0x10000>; 440 #address-cells = <1>; 441 #size-cells = <1>; 442 443 u2phy: usb2-phy@100 { 444 compatible = "rockchip,rk3328-usb2phy"; 445 reg = <0x100 0x10>; 446 #phy-cells = <1>; 447 status = "disabled"; 448 449 u2phy_host: host-port { 450 #phy-cells = <0>; 451 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 452 interrupt-names = "linestate"; 453 status = "disabled"; 454 }; 455 456 u2phy_otg: otg-port { 457 #phy-cells = <0>; 458 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "otg-bvalid", "otg-id", 462 "linestate"; 463 status = "disabled"; 464 }; 465 }; 466 }; 467 468 usb3phy_grf: syscon@ff460000 { 469 compatible = "rockchip,usb3phy-grf", "syscon"; 470 reg = <0x0 0xff460000 0x0 0x1000>; 471 }; 472 473 u3phy: usb3-phy@ff470000 { 474 compatible = "rockchip,rk3328-u3phy"; 475 reg = <0x0 0xff470000 0x0 0x0>; 476 rockchip,u3phygrf = <&usb3phy_grf>; 477 rockchip,grf = <&grf>; 478 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 479 interrupt-names = "linestate"; 480 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; 481 clock-names = "u3phy-otg", "u3phy-pipe"; 482 resets = <&cru SRST_USB3PHY_U2>, 483 <&cru SRST_USB3PHY_U3>, 484 <&cru SRST_USB3PHY_PIPE>, 485 <&cru SRST_USB3OTG_UTMI>, 486 <&cru SRST_USB3PHY_OTG_P>, 487 <&cru SRST_USB3PHY_PIPE_P>; 488 reset-names = "u3phy-u2-por", "u3phy-u3-por", 489 "u3phy-pipe-mac", "u3phy-utmi-mac", 490 "u3phy-utmi-apb", "u3phy-pipe-apb"; 491 #address-cells = <2>; 492 #size-cells = <2>; 493 ranges; 494 status = "disabled"; 495 496 u3phy_utmi: utmi@ff470000 { 497 reg = <0x0 0xff470000 0x0 0x8000>; 498 #phy-cells = <0>; 499 status = "disabled"; 500 }; 501 502 u3phy_pipe: pipe@ff478000 { 503 reg = <0x0 0xff478000 0x0 0x8000>; 504 #phy-cells = <0>; 505 status = "disabled"; 506 }; 507 }; 508 509 sdmmc: rksdmmc@ff500000 { 510 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 511 reg = <0x0 0xff500000 0x0 0x4000>; 512 max-frequency = <150000000>; 513 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 514 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 515 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 516 fifo-depth = <0x100>; 517 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 518 status = "disabled"; 519 }; 520 521 sdio: dwmmc@ff510000 { 522 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 523 reg = <0x0 0xff510000 0x0 0x4000>; 524 max-frequency = <150000000>; 525 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 526 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 527 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 528 fifo-depth = <0x100>; 529 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 530 status = "disabled"; 531 }; 532 533 emmc: rksdmmc@ff520000 { 534 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 535 reg = <0x0 0xff520000 0x0 0x4000>; 536 max-frequency = <150000000>; 537 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 538 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 539 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 540 fifo-depth = <0x100>; 541 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 542 status = "disabled"; 543 }; 544 545 gmac2io: ethernet@ff540000 { 546 compatible = "rockchip,rk3328-gmac"; 547 reg = <0x0 0xff540000 0x0 0x10000>; 548 rockchip,grf = <&grf>; 549 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 550 interrupt-names = "macirq"; 551 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 552 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 553 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 554 <&cru PCLK_MAC2IO>; 555 clock-names = "stmmaceth", "mac_clk_rx", 556 "mac_clk_tx", "clk_mac_ref", 557 "clk_mac_refout", "aclk_mac", 558 "pclk_mac"; 559 resets = <&cru SRST_GMAC2IO_A>; 560 reset-names = "stmmaceth"; 561 status = "disabled"; 562 }; 563 564 gmac2phy: ethernet@ff550000 { 565 compatible = "rockchip,rk3328-gmac"; 566 reg = <0x0 0xff550000 0x0 0x10000>; 567 rockchip,grf = <&grf>; 568 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 569 interrupt-names = "macirq"; 570 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 571 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 572 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 573 <&cru SCLK_MAC2PHY_OUT>; 574 clock-names = "stmmaceth", "mac_clk_rx", 575 "mac_clk_tx", "clk_mac_ref", 576 "aclk_mac", "pclk_mac", 577 "clk_macphy"; 578 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; 579 reset-names = "stmmaceth", "mac-phy"; 580 phy-mode = "rmii"; 581 phy-handle = <&phy>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 584 status = "disabled"; 585 586 mdio { 587 compatible = "snps,dwmac-mdio"; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 591 phy: phy@0 { 592 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 593 reg = <0>; 594 phy-is-integrated; 595 }; 596 }; 597 }; 598 599 usb_host0_ehci: usb@ff5c0000 { 600 compatible = "generic-ehci"; 601 reg = <0x0 0xff5c0000 0x0 0x10000>; 602 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 603 phys = <&u2phy_host>; 604 phy-names = "usb"; 605 status = "disabled"; 606 }; 607 608 usb_host0_ohci: usb@ff5d0000 { 609 compatible = "generic-ohci"; 610 reg = <0x0 0xff5d0000 0x0 0x10000>; 611 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 612 phys = <&u2phy_host>; 613 phy-names = "usb"; 614 status = "disabled"; 615 }; 616 617 usb20_otg: usb@ff580000 { 618 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 619 "snps,dwc2"; 620 reg = <0x0 0xff580000 0x0 0x40000>; 621 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 622 hnp-srp-disable; 623 dr_mode = "otg"; 624 phys = <&u2phy_otg>; 625 phy-names = "usb"; 626 status = "disabled"; 627 }; 628 629 sdmmc_ext: rksdmmc@ff5f0000 { 630 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 631 reg = <0x0 0xff5f0000 0x0 0x4000>; 632 max-frequency = <150000000>; 633 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 634 clock-names = "biu", "ciu"; 635 fifo-depth = <0x100>; 636 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 637 status = "disabled"; 638 }; 639 640 usbdrd3: usb@ff600000 { 641 compatible = "rockchip,rk3328-dwc3"; 642 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 643 <&cru ACLK_USB3OTG>; 644 clock-names = "ref_clk", "suspend_clk", 645 "bus_clk"; 646 #address-cells = <2>; 647 #size-cells = <2>; 648 ranges; 649 status = "disabled"; 650 651 usbdrd_dwc3: dwc3@ff600000 { 652 compatible = "snps,dwc3"; 653 reg = <0x0 0xff600000 0x0 0x100000>; 654 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 655 dr_mode = "host"; 656 phys = <&u3phy_utmi>, <&u3phy_pipe>; 657 phy-names = "usb2-phy", "usb3-phy"; 658 phy_type = "utmi_wide"; 659 snps,dis_enblslpm_quirk; 660 snps,dis-u2-freeclk-exists-quirk; 661 snps,dis_u2_susphy_quirk; 662 snps,dis-u3-autosuspend-quirk; 663 snps,dis_u3_susphy_quirk; 664 snps,dis-del-phy-power-chg-quirk; 665 snps,tx-ipgap-linecheck-dis-quirk; 666 snps,xhci-trb-ent-quirk; 667 status = "disabled"; 668 }; 669 }; 670 671 gic: interrupt-controller@ffb70000 { 672 compatible = "arm,gic-400"; 673 #interrupt-cells = <3>; 674 #address-cells = <0>; 675 interrupt-controller; 676 reg = <0x0 0xff811000 0 0x1000>, 677 <0x0 0xff812000 0 0x2000>, 678 <0x0 0xff814000 0 0x2000>, 679 <0x0 0xff816000 0 0x2000>; 680 interrupts = <GIC_PPI 9 681 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 682 }; 683 684 pinctrl: pinctrl { 685 compatible = "rockchip,rk3328-pinctrl"; 686 rockchip,grf = <&grf>; 687 #address-cells = <2>; 688 #size-cells = <2>; 689 ranges; 690 691 gpio0: gpio0@ff210000 { 692 compatible = "rockchip,gpio-bank"; 693 reg = <0x0 0xff210000 0x0 0x100>; 694 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&cru PCLK_GPIO0>; 696 697 gpio-controller; 698 #gpio-cells = <2>; 699 700 interrupt-controller; 701 #interrupt-cells = <2>; 702 }; 703 704 gpio1: gpio1@ff220000 { 705 compatible = "rockchip,gpio-bank"; 706 reg = <0x0 0xff220000 0x0 0x100>; 707 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&cru PCLK_GPIO1>; 709 710 gpio-controller; 711 #gpio-cells = <2>; 712 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 717 gpio2: gpio2@ff230000 { 718 compatible = "rockchip,gpio-bank"; 719 reg = <0x0 0xff230000 0x0 0x100>; 720 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&cru PCLK_GPIO2>; 722 723 gpio-controller; 724 #gpio-cells = <2>; 725 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 }; 729 730 gpio3: gpio3@ff240000 { 731 compatible = "rockchip,gpio-bank"; 732 reg = <0x0 0xff240000 0x0 0x100>; 733 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&cru PCLK_GPIO3>; 735 736 gpio-controller; 737 #gpio-cells = <2>; 738 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 }; 742 743 pcfg_pull_up: pcfg-pull-up { 744 bias-pull-up; 745 }; 746 747 pcfg_pull_down: pcfg-pull-down { 748 bias-pull-down; 749 }; 750 751 pcfg_pull_none: pcfg-pull-none { 752 bias-disable; 753 }; 754 755 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 756 bias-disable; 757 drive-strength = <2>; 758 }; 759 760 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 761 bias-pull-up; 762 drive-strength = <2>; 763 }; 764 765 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 766 bias-pull-up; 767 drive-strength = <4>; 768 }; 769 770 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 771 bias-disable; 772 drive-strength = <4>; 773 }; 774 775 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 776 bias-pull-down; 777 drive-strength = <4>; 778 }; 779 780 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 781 bias-disable; 782 drive-strength = <8>; 783 }; 784 785 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 786 bias-pull-up; 787 drive-strength = <8>; 788 }; 789 790 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 791 bias-disable; 792 drive-strength = <12>; 793 }; 794 795 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 796 bias-pull-up; 797 drive-strength = <12>; 798 }; 799 800 pcfg_output_high: pcfg-output-high { 801 output-high; 802 }; 803 804 pcfg_output_low: pcfg-output-low { 805 output-low; 806 }; 807 808 pcfg_input_high: pcfg-input-high { 809 bias-pull-up; 810 input-enable; 811 }; 812 813 pcfg_input: pcfg-input { 814 input-enable; 815 }; 816 817 i2c0 { 818 i2c0_xfer: i2c0-xfer { 819 rockchip,pins = 820 <2 24 RK_FUNC_1 &pcfg_pull_none>, 821 <2 25 RK_FUNC_1 &pcfg_pull_none>; 822 }; 823 }; 824 825 i2c1 { 826 i2c1_xfer: i2c1-xfer { 827 rockchip,pins = 828 <2 4 RK_FUNC_2 &pcfg_pull_none>, 829 <2 5 RK_FUNC_2 &pcfg_pull_none>; 830 }; 831 }; 832 833 i2c2 { 834 i2c2_xfer: i2c2-xfer { 835 rockchip,pins = 836 <2 13 RK_FUNC_1 &pcfg_pull_none>, 837 <2 14 RK_FUNC_1 &pcfg_pull_none>; 838 }; 839 }; 840 841 i2c3 { 842 i2c3_xfer: i2c3-xfer { 843 rockchip,pins = 844 <0 5 RK_FUNC_2 &pcfg_pull_none>, 845 <0 6 RK_FUNC_2 &pcfg_pull_none>; 846 }; 847 i2c3_gpio: i2c3-gpio { 848 rockchip,pins = 849 <0 5 RK_FUNC_GPIO &pcfg_pull_none>, 850 <0 6 RK_FUNC_GPIO &pcfg_pull_none>; 851 }; 852 }; 853 854 hdmi_i2c { 855 hdmii2c_xfer: hdmii2c-xfer { 856 rockchip,pins = 857 <0 5 RK_FUNC_1 &pcfg_pull_none>, 858 <0 6 RK_FUNC_1 &pcfg_pull_none>; 859 }; 860 }; 861 862 uart0 { 863 uart0_xfer: uart0-xfer { 864 rockchip,pins = 865 <1 9 RK_FUNC_1 &pcfg_pull_up>, 866 <1 8 RK_FUNC_1 &pcfg_pull_up>; 867 }; 868 869 uart0_cts: uart0-cts { 870 rockchip,pins = 871 <1 11 RK_FUNC_1 &pcfg_pull_none>; 872 }; 873 874 uart0_rts: uart0-rts { 875 rockchip,pins = 876 <1 10 RK_FUNC_1 &pcfg_pull_none>; 877 }; 878 879 uart0_rts_gpio: uart0-rts-gpio { 880 rockchip,pins = 881 <1 10 RK_FUNC_GPIO &pcfg_pull_none>; 882 }; 883 }; 884 885 uart1 { 886 uart1_xfer: uart1-xfer { 887 rockchip,pins = 888 <3 4 RK_FUNC_4 &pcfg_pull_up>, 889 <3 6 RK_FUNC_4 &pcfg_pull_up>; 890 }; 891 892 uart1_cts: uart1-cts { 893 rockchip,pins = 894 <3 7 RK_FUNC_4 &pcfg_pull_none>; 895 }; 896 897 uart1_rts: uart1-rts { 898 rockchip,pins = 899 <3 5 RK_FUNC_4 &pcfg_pull_none>; 900 }; 901 902 uart1_rts_gpio: uart1-rts-gpio { 903 rockchip,pins = 904 <3 5 RK_FUNC_GPIO &pcfg_pull_none>; 905 }; 906 }; 907 908 uart2-0 { 909 uart2m0_xfer: uart2m0-xfer { 910 rockchip,pins = 911 <1 0 RK_FUNC_2 &pcfg_pull_up>, 912 <1 1 RK_FUNC_2 &pcfg_pull_up>; 913 }; 914 }; 915 916 uart2-1 { 917 uart2m1_xfer: uart2m1-xfer { 918 rockchip,pins = 919 <2 0 RK_FUNC_1 &pcfg_pull_up>, 920 <2 1 RK_FUNC_1 &pcfg_pull_up>; 921 }; 922 }; 923 924 spi0-0 { 925 spi0m0_clk: spi0m0-clk { 926 rockchip,pins = 927 <2 8 RK_FUNC_1 &pcfg_pull_up>; 928 }; 929 930 spi0m0_cs0: spi0m0-cs0 { 931 rockchip,pins = 932 <2 11 RK_FUNC_1 &pcfg_pull_up>; 933 }; 934 935 spi0m0_tx: spi0m0-tx { 936 rockchip,pins = 937 <2 9 RK_FUNC_1 &pcfg_pull_up>; 938 }; 939 940 spi0m0_rx: spi0m0-rx { 941 rockchip,pins = 942 <2 10 RK_FUNC_1 &pcfg_pull_up>; 943 }; 944 945 spi0m0_cs1: spi0m0-cs1 { 946 rockchip,pins = 947 <2 12 RK_FUNC_1 &pcfg_pull_up>; 948 }; 949 }; 950 951 spi0-1 { 952 spi0m1_clk: spi0m1-clk { 953 rockchip,pins = 954 <3 23 RK_FUNC_2 &pcfg_pull_up>; 955 }; 956 957 spi0m1_cs0: spi0m1-cs0 { 958 rockchip,pins = 959 <3 26 RK_FUNC_2 &pcfg_pull_up>; 960 }; 961 962 spi0m1_tx: spi0m1-tx { 963 rockchip,pins = 964 <3 25 RK_FUNC_2 &pcfg_pull_up>; 965 }; 966 967 spi0m1_rx: spi0m1-rx { 968 rockchip,pins = 969 <3 24 RK_FUNC_2 &pcfg_pull_up>; 970 }; 971 972 spi0m1_cs1: spi0m1-cs1 { 973 rockchip,pins = 974 <3 27 RK_FUNC_2 &pcfg_pull_up>; 975 }; 976 }; 977 978 spi0-2 { 979 spi0m2_clk: spi0m2-clk { 980 rockchip,pins = 981 <3 0 RK_FUNC_4 &pcfg_pull_up>; 982 }; 983 984 spi0m2_cs0: spi0m2-cs0 { 985 rockchip,pins = 986 <3 8 RK_FUNC_3 &pcfg_pull_up>; 987 }; 988 989 spi0m2_tx: spi0m2-tx { 990 rockchip,pins = 991 <3 1 RK_FUNC_4 &pcfg_pull_up>; 992 }; 993 994 spi0m2_rx: spi0m2-rx { 995 rockchip,pins = 996 <3 2 RK_FUNC_4 &pcfg_pull_up>; 997 }; 998 }; 999 1000 i2s1 { 1001 i2s1_mclk: i2s1-mclk { 1002 rockchip,pins = 1003 <2 15 RK_FUNC_1 &pcfg_pull_none>; 1004 }; 1005 1006 i2s1_sclk: i2s1-sclk { 1007 rockchip,pins = 1008 <2 18 RK_FUNC_1 &pcfg_pull_none>; 1009 }; 1010 1011 i2s1_lrckrx: i2s1-lrckrx { 1012 rockchip,pins = 1013 <2 16 RK_FUNC_1 &pcfg_pull_none>; 1014 }; 1015 1016 i2s1_lrcktx: i2s1-lrcktx { 1017 rockchip,pins = 1018 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1019 }; 1020 1021 i2s1_sdi: i2s1-sdi { 1022 rockchip,pins = 1023 <2 19 RK_FUNC_1 &pcfg_pull_none>; 1024 }; 1025 1026 i2s1_sdo: i2s1-sdo { 1027 rockchip,pins = 1028 <2 23 RK_FUNC_1 &pcfg_pull_none>; 1029 }; 1030 1031 i2s1_sdio1: i2s1-sdio1 { 1032 rockchip,pins = 1033 <2 20 RK_FUNC_1 &pcfg_pull_none>; 1034 }; 1035 1036 i2s1_sdio2: i2s1-sdio2 { 1037 rockchip,pins = 1038 <2 21 RK_FUNC_1 &pcfg_pull_none>; 1039 }; 1040 1041 i2s1_sdio3: i2s1-sdio3 { 1042 rockchip,pins = 1043 <2 22 RK_FUNC_1 &pcfg_pull_none>; 1044 }; 1045 1046 i2s1_sleep: i2s1-sleep { 1047 rockchip,pins = 1048 <2 15 RK_FUNC_GPIO &pcfg_input_high>, 1049 <2 16 RK_FUNC_GPIO &pcfg_input_high>, 1050 <2 17 RK_FUNC_GPIO &pcfg_input_high>, 1051 <2 18 RK_FUNC_GPIO &pcfg_input_high>, 1052 <2 19 RK_FUNC_GPIO &pcfg_input_high>, 1053 <2 20 RK_FUNC_GPIO &pcfg_input_high>, 1054 <2 21 RK_FUNC_GPIO &pcfg_input_high>, 1055 <2 22 RK_FUNC_GPIO &pcfg_input_high>, 1056 <2 23 RK_FUNC_GPIO &pcfg_input_high>; 1057 }; 1058 }; 1059 1060 i2s2-0 { 1061 i2s2m0_mclk: i2s2m0-mclk { 1062 rockchip,pins = 1063 <1 21 RK_FUNC_1 &pcfg_pull_none>; 1064 }; 1065 1066 i2s2m0_sclk: i2s2m0-sclk { 1067 rockchip,pins = 1068 <1 22 RK_FUNC_1 &pcfg_pull_none>; 1069 }; 1070 1071 i2s2m0_lrckrx: i2s2m0-lrckrx { 1072 rockchip,pins = 1073 <1 26 RK_FUNC_1 &pcfg_pull_none>; 1074 }; 1075 1076 i2s2m0_lrcktx: i2s2m0-lrcktx { 1077 rockchip,pins = 1078 <1 23 RK_FUNC_1 &pcfg_pull_none>; 1079 }; 1080 1081 i2s2m0_sdi: i2s2m0-sdi { 1082 rockchip,pins = 1083 <1 24 RK_FUNC_1 &pcfg_pull_none>; 1084 }; 1085 1086 i2s2m0_sdo: i2s2m0-sdo { 1087 rockchip,pins = 1088 <1 25 RK_FUNC_1 &pcfg_pull_none>; 1089 }; 1090 1091 i2s2m0_sleep: i2s2m0-sleep { 1092 rockchip,pins = 1093 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 1094 <1 22 RK_FUNC_GPIO &pcfg_input_high>, 1095 <1 26 RK_FUNC_GPIO &pcfg_input_high>, 1096 <1 23 RK_FUNC_GPIO &pcfg_input_high>, 1097 <1 24 RK_FUNC_GPIO &pcfg_input_high>, 1098 <1 25 RK_FUNC_GPIO &pcfg_input_high>; 1099 }; 1100 }; 1101 1102 i2s2-1 { 1103 i2s2m1_mclk: i2s2m1-mclk { 1104 rockchip,pins = 1105 <1 21 RK_FUNC_1 &pcfg_pull_none>; 1106 }; 1107 1108 i2s2m1_sclk: i2s2m1-sclk { 1109 rockchip,pins = 1110 <3 0 RK_FUNC_6 &pcfg_pull_none>; 1111 }; 1112 1113 i2s2m1_lrckrx: i2sm1-lrckrx { 1114 rockchip,pins = 1115 <3 8 RK_FUNC_6 &pcfg_pull_none>; 1116 }; 1117 1118 i2s2m1_lrcktx: i2s2m1-lrcktx { 1119 rockchip,pins = 1120 <3 8 RK_FUNC_4 &pcfg_pull_none>; 1121 }; 1122 1123 i2s2m1_sdi: i2s2m1-sdi { 1124 rockchip,pins = 1125 <3 2 RK_FUNC_6 &pcfg_pull_none>; 1126 }; 1127 1128 i2s2m1_sdo: i2s2m1-sdo { 1129 rockchip,pins = 1130 <3 1 RK_FUNC_6 &pcfg_pull_none>; 1131 }; 1132 1133 i2s2m1_sleep: i2s2m1-sleep { 1134 rockchip,pins = 1135 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 1136 <3 0 RK_FUNC_GPIO &pcfg_input_high>, 1137 <3 8 RK_FUNC_GPIO &pcfg_input_high>, 1138 <3 2 RK_FUNC_GPIO &pcfg_input_high>, 1139 <3 1 RK_FUNC_GPIO &pcfg_input_high>; 1140 }; 1141 }; 1142 1143 spdif-0 { 1144 spdifm0_tx: spdifm0-tx { 1145 rockchip,pins = 1146 <0 27 RK_FUNC_1 &pcfg_pull_none>; 1147 }; 1148 }; 1149 1150 spdif-1 { 1151 spdifm1_tx: spdifm1-tx { 1152 rockchip,pins = 1153 <2 17 RK_FUNC_2 &pcfg_pull_none>; 1154 }; 1155 }; 1156 1157 spdif-2 { 1158 spdifm2_tx: spdifm2-tx { 1159 rockchip,pins = 1160 <0 2 RK_FUNC_2 &pcfg_pull_none>; 1161 }; 1162 }; 1163 1164 sdmmc0-0 { 1165 sdmmc0m0_pwren: sdmmc0m0-pwren { 1166 rockchip,pins = 1167 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1168 }; 1169 1170 sdmmc0m0_gpio: sdmmc0m0-gpio { 1171 rockchip,pins = 1172 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1173 }; 1174 }; 1175 1176 sdmmc0-1 { 1177 sdmmc0m1_pwren: sdmmc0m1-pwren { 1178 rockchip,pins = 1179 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; 1180 }; 1181 1182 sdmmc0m1_gpio: sdmmc0m1-gpio { 1183 rockchip,pins = 1184 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1185 }; 1186 }; 1187 1188 sdmmc0 { 1189 sdmmc0_clk: sdmmc0-clk { 1190 rockchip,pins = 1191 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1192 }; 1193 1194 sdmmc0_cmd: sdmmc0-cmd { 1195 rockchip,pins = 1196 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; 1197 }; 1198 1199 sdmmc0_dectn: sdmmc0-dectn { 1200 rockchip,pins = 1201 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1202 }; 1203 1204 sdmmc0_wrprt: sdmmc0-wrprt { 1205 rockchip,pins = 1206 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1207 }; 1208 1209 sdmmc0_bus1: sdmmc0-bus1 { 1210 rockchip,pins = 1211 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; 1212 }; 1213 1214 sdmmc0_bus4: sdmmc0-bus4 { 1215 rockchip,pins = 1216 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, 1217 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, 1218 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1219 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; 1220 }; 1221 1222 sdmmc0_gpio: sdmmc0-gpio { 1223 rockchip,pins = 1224 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1225 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1226 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1227 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1228 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1229 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1230 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1231 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1232 }; 1233 }; 1234 1235 sdmmc0ext { 1236 sdmmc0ext_clk: sdmmc0ext-clk { 1237 rockchip,pins = 1238 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; 1239 }; 1240 1241 sdmmc0ext_cmd: sdmmc0ext-cmd { 1242 rockchip,pins = 1243 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; 1244 }; 1245 1246 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1247 rockchip,pins = 1248 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; 1249 }; 1250 1251 sdmmc0ext_dectn: sdmmc0ext-dectn { 1252 rockchip,pins = 1253 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; 1254 }; 1255 1256 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1257 rockchip,pins = 1258 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; 1259 }; 1260 1261 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1262 rockchip,pins = 1263 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, 1264 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, 1265 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, 1266 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; 1267 }; 1268 1269 sdmmc0ext_gpio: sdmmc0ext-gpio { 1270 rockchip,pins = 1271 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1272 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1273 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1274 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1275 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1276 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1277 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1278 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1279 }; 1280 }; 1281 1282 sdmmc1 { 1283 sdmmc1_clk: sdmmc1-clk { 1284 rockchip,pins = 1285 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1286 }; 1287 1288 sdmmc1_cmd: sdmmc1-cmd { 1289 rockchip,pins = 1290 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; 1291 }; 1292 1293 sdmmc1_pwren: sdmmc1-pwren { 1294 rockchip,pins = 1295 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; 1296 }; 1297 1298 sdmmc1_wrprt: sdmmc1-wrprt { 1299 rockchip,pins = 1300 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; 1301 }; 1302 1303 sdmmc1_dectn: sdmmc1-dectn { 1304 rockchip,pins = 1305 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; 1306 }; 1307 1308 sdmmc1_bus1: sdmmc1-bus1 { 1309 rockchip,pins = 1310 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; 1311 }; 1312 1313 sdmmc1_bus4: sdmmc1-bus4 { 1314 rockchip,pins = 1315 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, 1316 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, 1317 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, 1318 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; 1319 }; 1320 1321 sdmmc1_gpio: sdmmc1-gpio { 1322 rockchip,pins = 1323 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1324 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1325 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1326 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1327 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1328 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1329 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1330 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1331 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1332 }; 1333 }; 1334 1335 emmc { 1336 emmc_clk: emmc-clk { 1337 rockchip,pins = 1338 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; 1339 }; 1340 1341 emmc_cmd: emmc-cmd { 1342 rockchip,pins = 1343 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; 1344 }; 1345 1346 emmc_pwren: emmc-pwren { 1347 rockchip,pins = 1348 <3 22 RK_FUNC_2 &pcfg_pull_none>; 1349 }; 1350 1351 emmc_rstnout: emmc-rstnout { 1352 rockchip,pins = 1353 <3 20 RK_FUNC_2 &pcfg_pull_none>; 1354 }; 1355 1356 emmc_bus1: emmc-bus1 { 1357 rockchip,pins = 1358 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; 1359 }; 1360 1361 emmc_bus4: emmc-bus4 { 1362 rockchip,pins = 1363 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1364 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1365 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1366 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; 1367 }; 1368 1369 emmc_bus8: emmc-bus8 { 1370 rockchip,pins = 1371 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1372 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1373 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1374 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, 1375 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, 1376 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, 1377 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, 1378 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; 1379 }; 1380 }; 1381 1382 pwm0 { 1383 pwm0_pin: pwm0-pin { 1384 rockchip,pins = 1385 <2 4 RK_FUNC_1 &pcfg_pull_none>; 1386 }; 1387 }; 1388 1389 pwm1 { 1390 pwm1_pin: pwm1-pin { 1391 rockchip,pins = 1392 <2 5 RK_FUNC_1 &pcfg_pull_none>; 1393 }; 1394 }; 1395 1396 pwm2 { 1397 pwm2_pin: pwm2-pin { 1398 rockchip,pins = 1399 <2 6 RK_FUNC_1 &pcfg_pull_none>; 1400 }; 1401 }; 1402 1403 pwmir { 1404 pwmir_pin: pwmir-pin { 1405 rockchip,pins = 1406 <2 2 RK_FUNC_1 &pcfg_pull_none>; 1407 }; 1408 }; 1409 1410 gmac-0 { 1411 rgmiim0_pins: rgmiim0-pins { 1412 rockchip,pins = 1413 /* mac_txclk */ 1414 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1415 /* mac_rxclk */ 1416 <0 10 RK_FUNC_1 &pcfg_pull_none>, 1417 /* mac_mdio */ 1418 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1419 /* mac_txen */ 1420 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1421 /* mac_clk */ 1422 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1423 /* mac_rxdv */ 1424 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1425 /* mac_mdc */ 1426 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1427 /* mac_rxd1 */ 1428 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1429 /* mac_rxd0 */ 1430 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1431 /* mac_txd1 */ 1432 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1433 /* mac_txd0 */ 1434 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, 1435 /* mac_rxd3 */ 1436 <0 20 RK_FUNC_1 &pcfg_pull_none>, 1437 /* mac_rxd2 */ 1438 <0 21 RK_FUNC_1 &pcfg_pull_none>, 1439 /* mac_txd3 */ 1440 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, 1441 /* mac_txd2 */ 1442 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; 1443 }; 1444 1445 rmiim0_pins: rmiim0-pins { 1446 rockchip,pins = 1447 /* mac_mdio */ 1448 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1449 /* mac_txen */ 1450 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1451 /* mac_clk */ 1452 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1453 /* mac_rxer */ 1454 <0 13 RK_FUNC_1 &pcfg_pull_none>, 1455 /* mac_rxdv */ 1456 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1457 /* mac_mdc */ 1458 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1459 /* mac_rxd1 */ 1460 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1461 /* mac_rxd0 */ 1462 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1463 /* mac_txd1 */ 1464 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1465 /* mac_txd0 */ 1466 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; 1467 }; 1468 }; 1469 1470 gmac-1 { 1471 rgmiim1_pins: rgmiim1-pins { 1472 rockchip,pins = 1473 /* mac_txclk */ 1474 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, 1475 /* mac_rxclk */ 1476 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, 1477 /* mac_mdio */ 1478 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1479 /* mac_txen */ 1480 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1481 /* mac_clk */ 1482 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1483 /* mac_rxdv */ 1484 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1485 /* mac_mdc */ 1486 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1487 /* mac_rxd1 */ 1488 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1489 /* mac_rxd0 */ 1490 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1491 /* mac_txd1 */ 1492 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1493 /* mac_txd0 */ 1494 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1495 /* mac_rxd3 */ 1496 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, 1497 /* mac_rxd2 */ 1498 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, 1499 /* mac_txd3 */ 1500 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, 1501 /* mac_txd2 */ 1502 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, 1503 1504 /* mac_txclk */ 1505 <0 8 RK_FUNC_1 &pcfg_pull_none>, 1506 /* mac_txen */ 1507 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1508 /* mac_clk */ 1509 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1510 /* mac_txd1 */ 1511 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1512 /* mac_txd0 */ 1513 <0 17 RK_FUNC_1 &pcfg_pull_none>, 1514 /* mac_txd3 */ 1515 <0 23 RK_FUNC_1 &pcfg_pull_none>, 1516 /* mac_txd2 */ 1517 <0 22 RK_FUNC_1 &pcfg_pull_none>; 1518 }; 1519 1520 rmiim1_pins: rmiim1-pins { 1521 rockchip,pins = 1522 /* mac_mdio */ 1523 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1524 /* mac_txen */ 1525 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1526 /* mac_clk */ 1527 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1528 /* mac_rxer */ 1529 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, 1530 /* mac_rxdv */ 1531 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1532 /* mac_mdc */ 1533 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1534 /* mac_rxd1 */ 1535 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1536 /* mac_rxd0 */ 1537 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1538 /* mac_txd1 */ 1539 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1540 /* mac_txd0 */ 1541 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1542 1543 /* mac_mdio */ 1544 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1545 /* mac_txen */ 1546 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1547 /* mac_clk */ 1548 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1549 /* mac_mdc */ 1550 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1551 /* mac_txd1 */ 1552 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1553 /* mac_txd0 */ 1554 <0 17 RK_FUNC_1 &pcfg_pull_none>; 1555 }; 1556 }; 1557 1558 gmac2phy { 1559 fephyled_speed100: fephyled-speed100 { 1560 rockchip,pins = 1561 <0 31 RK_FUNC_1 &pcfg_pull_none>; 1562 }; 1563 1564 fephyled_speed10: fephyled-speed10 { 1565 rockchip,pins = 1566 <0 30 RK_FUNC_1 &pcfg_pull_none>; 1567 }; 1568 1569 fephyled_duplex: fephyled-duplex { 1570 rockchip,pins = 1571 <0 30 RK_FUNC_2 &pcfg_pull_none>; 1572 }; 1573 1574 fephyled_rxm0: fephyled-rxm0 { 1575 rockchip,pins = 1576 <0 29 RK_FUNC_1 &pcfg_pull_none>; 1577 }; 1578 1579 fephyled_txm0: fephyled-txm0 { 1580 rockchip,pins = 1581 <0 29 RK_FUNC_2 &pcfg_pull_none>; 1582 }; 1583 1584 fephyled_linkm0: fephyled-linkm0 { 1585 rockchip,pins = 1586 <0 28 RK_FUNC_1 &pcfg_pull_none>; 1587 }; 1588 1589 fephyled_rxm1: fephyled-rxm1 { 1590 rockchip,pins = 1591 <2 25 RK_FUNC_2 &pcfg_pull_none>; 1592 }; 1593 1594 fephyled_txm1: fephyled-txm1 { 1595 rockchip,pins = 1596 <2 25 RK_FUNC_3 &pcfg_pull_none>; 1597 }; 1598 1599 fephyled_linkm1: fephyled-linkm1 { 1600 rockchip,pins = 1601 <2 24 RK_FUNC_2 &pcfg_pull_none>; 1602 }; 1603 }; 1604 1605 tsadc_pin { 1606 tsadc_int: tsadc-int { 1607 rockchip,pins = 1608 <2 13 RK_FUNC_2 &pcfg_pull_none>; 1609 }; 1610 tsadc_gpio: tsadc-gpio { 1611 rockchip,pins = 1612 <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 1613 }; 1614 }; 1615 1616 hdmi_pin { 1617 hdmi_cec: hdmi-cec { 1618 rockchip,pins = 1619 <0 3 RK_FUNC_1 &pcfg_pull_none>; 1620 }; 1621 1622 hdmi_hpd: hdmi-hpd { 1623 rockchip,pins = 1624 <0 4 RK_FUNC_1 &pcfg_pull_down>; 1625 }; 1626 }; 1627 1628 cif-0 { 1629 dvp_d2d9_m0:dvp-d2d9-m0 { 1630 rockchip,pins = 1631 /* cif_d0 */ 1632 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1633 /* cif_d1 */ 1634 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1635 /* cif_d2 */ 1636 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1637 /* cif_d3 */ 1638 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1639 /* cif_d4 */ 1640 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1641 /* cif_d5m0 */ 1642 <3 9 RK_FUNC_2 &pcfg_pull_none>, 1643 /* cif_d6m0 */ 1644 <3 10 RK_FUNC_2 &pcfg_pull_none>, 1645 /* cif_d7m0 */ 1646 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1647 /* cif_href */ 1648 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1649 /* cif_vsync */ 1650 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1651 /* cif_clkoutm0 */ 1652 <3 3 RK_FUNC_2 &pcfg_pull_none>, 1653 /* cif_clkin */ 1654 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1655 }; 1656 }; 1657 1658 cif-1 { 1659 dvp_d2d9_m1:dvp-d2d9-m1 { 1660 rockchip,pins = 1661 /* cif_d0 */ 1662 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1663 /* cif_d1 */ 1664 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1665 /* cif_d2 */ 1666 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1667 /* cif_d3 */ 1668 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1669 /* cif_d4 */ 1670 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1671 /* cif_d5m1 */ 1672 <2 16 RK_FUNC_4 &pcfg_pull_none>, 1673 /* cif_d6m1 */ 1674 <2 17 RK_FUNC_4 &pcfg_pull_none>, 1675 /* cif_d7m1 */ 1676 <2 18 RK_FUNC_4 &pcfg_pull_none>, 1677 /* cif_href */ 1678 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1679 /* cif_vsync */ 1680 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1681 /* cif_clkoutm1 */ 1682 <2 15 RK_FUNC_4 &pcfg_pull_none>, 1683 /* cif_clkin */ 1684 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1685 }; 1686 }; 1687 }; 1688}; 1689