1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * (C) Copyright 2018 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "px30.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun&rgb { 9*4882a593Smuzhiyun phys = <&video_phy>; 10*4882a593Smuzhiyun phy-names = "phy"; 11*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 12*4882a593Smuzhiyun pinctrl-0 = <&lcdc_m1_rgb_pins>; 13*4882a593Smuzhiyun pinctrl-1 = <&lcdc_m1_sleep_pins>; 14*4882a593Smuzhiyun}; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun&pinctrl { 17*4882a593Smuzhiyun lcdc { 18*4882a593Smuzhiyun lcdc_m1_rgb_pins: lcdc-m1-rgb-pins { 19*4882a593Smuzhiyun rockchip,pins = 20*4882a593Smuzhiyun <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ 21*4882a593Smuzhiyun <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ 22*4882a593Smuzhiyun <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ 23*4882a593Smuzhiyun <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ 24*4882a593Smuzhiyun <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ 25*4882a593Smuzhiyun <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ 26*4882a593Smuzhiyun <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ 27*4882a593Smuzhiyun <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ 28*4882a593Smuzhiyun <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ 29*4882a593Smuzhiyun <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ 30*4882a593Smuzhiyun <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ 31*4882a593Smuzhiyun <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ 32*4882a593Smuzhiyun <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ 33*4882a593Smuzhiyun <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ 34*4882a593Smuzhiyun <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ 35*4882a593Smuzhiyun <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ 36*4882a593Smuzhiyun <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ 37*4882a593Smuzhiyun <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun lcdc_m1_sleep_pins: lcdc-m1-sleep-pins { 41*4882a593Smuzhiyun rockchip,pins = 42*4882a593Smuzhiyun <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ 43*4882a593Smuzhiyun <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ 44*4882a593Smuzhiyun <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ 45*4882a593Smuzhiyun <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ 46*4882a593Smuzhiyun <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ 47*4882a593Smuzhiyun <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ 48*4882a593Smuzhiyun <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ 49*4882a593Smuzhiyun <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ 50*4882a593Smuzhiyun <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ 51*4882a593Smuzhiyun <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ 52*4882a593Smuzhiyun <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ 53*4882a593Smuzhiyun <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ 54*4882a593Smuzhiyun <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ 55*4882a593Smuzhiyun <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ 56*4882a593Smuzhiyun <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ 57*4882a593Smuzhiyun <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ 58*4882a593Smuzhiyun <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ 59*4882a593Smuzhiyun <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun}; 63