1/* 2 * Device tree file for Phytec phyCORE-RK3288 SoM 3 * Copyright (C) 2017 PHYTEC Messtechnik GmbH 4 * Author: Wadim Egorov <w.egorov@phytec.de> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/net/ti-dp83867.h> 46#include "rk3288.dtsi" 47#include "rk3288-u-boot.dtsi" 48 49/ { 50 model = "Phytec RK3288 phyCORE"; 51 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; 52 53 /* 54 * Set the minimum memory size here and 55 * let the bootloader set the real size. 56 */ 57 memory { 58 device_type = "memory"; 59 reg = <0 0x8000000>; 60 }; 61 62 aliases { 63 rtc0 = &i2c_rtc; 64 rtc1 = &rk818; 65 eeprom0 = &i2c_eeprom_id; 66 }; 67 68 ext_gmac: external-gmac-clock { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <125000000>; 72 clock-output-names = "ext_gmac"; 73 }; 74 75 io_domains: io_domains { 76 compatible = "rockchip,rk3288-io-voltage-domain"; 77 78 status = "okay"; 79 sdcard-supply = <&vdd_io_sd>; 80 flash0-supply = <&vdd_emmc_io>; 81 flash1-supply = <&vdd_misc_1v8>; 82 gpio1830-supply = <&vdd_3v3_io>; 83 gpio30-supply = <&vdd_3v3_io>; 84 bb-supply = <&vdd_3v3_io>; 85 dvp-supply = <&vdd_3v3_io>; 86 lcdc-supply = <&vdd_3v3_io>; 87 wifi-supply = <&vdd_3v3_io>; 88 audio-supply = <&vdd_3v3_io>; 89 }; 90 91 leds: user-leds { 92 compatible = "gpio-leds"; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&user_led>; 95 96 user { 97 label = "green_led"; 98 gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 99 linux,default-trigger = "heartbeat"; 100 default-state = "keep"; 101 }; 102 }; 103 104 vdd_emmc_io: vdd-emmc-io { 105 compatible = "regulator-fixed"; 106 regulator-name = "vdd_emmc_io"; 107 regulator-min-microvolt = <1800000>; 108 regulator-max-microvolt = <1800000>; 109 vin-supply = <&vdd_3v3_io>; 110 }; 111 112 vdd_in_otg_out: vdd-in-otg-out { 113 compatible = "regulator-fixed"; 114 regulator-name = "vdd_in_otg_out"; 115 regulator-always-on; 116 regulator-boot-on; 117 regulator-min-microvolt = <5000000>; 118 regulator-max-microvolt = <5000000>; 119 }; 120 121 vdd_misc_1v8: vdd-misc-1v8 { 122 compatible = "regulator-fixed"; 123 regulator-name = "vdd_misc_1v8"; 124 regulator-always-on; 125 regulator-boot-on; 126 regulator-min-microvolt = <1800000>; 127 regulator-max-microvolt = <1800000>; 128 }; 129}; 130 131&cpu0 { 132 cpu0-supply = <&vdd_cpu>; 133 operating-points = < 134 /* KHz uV */ 135 1800000 1400000 136 1608000 1350000 137 1512000 1300000 138 1416000 1200000 139 1200000 1100000 140 1008000 1050000 141 816000 1000000 142 696000 950000 143 600000 900000 144 408000 900000 145 312000 900000 146 216000 900000 147 126000 900000 148 >; 149}; 150 151&emmc { 152 status = "okay"; 153 u-boot,dm-pre-reloc; 154 155 bus-width = <8>; 156 cap-mmc-highspeed; 157 disable-wp; 158 non-removable; 159 num-slots = <1>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; 162 vmmc-supply = <&vdd_3v3_io>; 163 vqmmc-supply = <&vdd_emmc_io>; 164}; 165 166&gmac { 167 assigned-clocks = <&cru SCLK_MAC>; 168 assigned-clock-parents = <&ext_gmac>; 169 clock_in_out = "input"; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>; 172 phy-handle = <&phy0>; 173 phy-supply = <&vdd_eth_2v5>; 174 phy-mode = "rgmii-id"; 175 snps,reset-active-low; 176 snps,reset-delays-us = <0 10000 1000000>; 177 snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; 178 tx_delay = <0x0>; 179 rx_delay = <0x0>; 180 181 mdio0 { 182 compatible = "snps,dwmac-mdio"; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 186 phy0: ethernet-phy@0 { 187 compatible = "ethernet-phy-ieee802.3-c22"; 188 reg = <0>; 189 interrupt-parent = <&gpio4>; 190 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 191 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 192 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 193 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 194 enet-phy-lane-no-swap; 195 }; 196 }; 197}; 198 199&hdmi { 200 ddc-i2c-bus = <&i2c5>; 201}; 202 203&i2c0 { 204 status = "okay"; 205 u-boot,dm-pre-reloc; 206 207 clock-frequency = <400000>; 208 209 rk818: pmic@1c { 210 status = "okay"; 211 compatible = "rockchip,rk818"; 212 reg = <0x1c>; 213 interrupt-parent = <&gpio0>; 214 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pmic_int>; 217 rockchip,system-power-controller; 218 wakeup-source; 219 #clock-cells = <1>; 220 u-boot,dm-pre-reloc; 221 222 vcc1-supply = <&vdd_sys>; 223 vcc2-supply = <&vdd_sys>; 224 vcc3-supply = <&vdd_sys>; 225 vcc4-supply = <&vdd_sys>; 226 boost-supply = <&vdd_in_otg_out>; 227 vcc6-supply = <&vdd_sys>; 228 vcc7-supply = <&vdd_misc_1v8>; 229 vcc8-supply = <&vdd_misc_1v8>; 230 vcc9-supply = <&vdd_3v3_io>; 231 vddio-supply = <&vdd_3v3_io>; 232 233 regulators { 234 u-boot,dm-pre-reloc; 235 vdd_log: DCDC_REG1 { 236 regulator-name = "vdd_log"; 237 regulator-always-on; 238 regulator-boot-on; 239 regulator-min-microvolt = <1100000>; 240 regulator-max-microvolt = <1100000>; 241 regulator-state-mem { 242 regulator-off-in-suspend; 243 }; 244 }; 245 246 vdd_gpu: DCDC_REG2 { 247 regulator-name = "vdd_gpu"; 248 regulator-always-on; 249 regulator-boot-on; 250 regulator-min-microvolt = <800000>; 251 regulator-max-microvolt = <1250000>; 252 regulator-state-mem { 253 regulator-on-in-suspend; 254 regulator-suspend-microvolt = <1000000>; 255 }; 256 }; 257 258 vcc_ddr: DCDC_REG3 { 259 regulator-name = "vcc_ddr"; 260 regulator-always-on; 261 regulator-boot-on; 262 regulator-state-mem { 263 regulator-on-in-suspend; 264 }; 265 }; 266 267 vdd_3v3_io: DCDC_REG4 { 268 regulator-name = "vdd_3v3_io"; 269 regulator-always-on; 270 regulator-boot-on; 271 regulator-min-microvolt = <3300000>; 272 regulator-max-microvolt = <3300000>; 273 regulator-state-mem { 274 regulator-on-in-suspend; 275 regulator-suspend-microvolt = <3300000>; 276 }; 277 }; 278 279 vdd_sys: DCDC_BOOST { 280 regulator-name = "vdd_sys"; 281 regulator-always-on; 282 regulator-boot-on; 283 regulator-min-microvolt = <5000000>; 284 regulator-max-microvolt = <5000000>; 285 regulator-state-mem { 286 regulator-on-in-suspend; 287 regulator-suspend-microvolt = <5000000>; 288 }; 289 }; 290 291 /* vcc9 */ 292 vdd_sd: SWITCH_REG { 293 regulator-name = "vdd_sd"; 294 regulator-always-on; 295 regulator-boot-on; 296 regulator-state-mem { 297 regulator-off-in-suspend; 298 }; 299 }; 300 301 /* vcc6 */ 302 vdd_eth_2v5: LDO_REG2 { 303 regulator-name = "vdd_eth_2v5"; 304 regulator-always-on; 305 regulator-boot-on; 306 regulator-min-microvolt = <2500000>; 307 regulator-max-microvolt = <2500000>; 308 regulator-state-mem { 309 regulator-on-in-suspend; 310 regulator-suspend-microvolt = <2500000>; 311 }; 312 }; 313 314 /* vcc7 */ 315 vdd_1v0: LDO_REG3 { 316 regulator-name = "vdd_1v0"; 317 regulator-always-on; 318 regulator-boot-on; 319 regulator-min-microvolt = <1000000>; 320 regulator-max-microvolt = <1000000>; 321 regulator-state-mem { 322 regulator-on-in-suspend; 323 regulator-suspend-microvolt = <1000000>; 324 }; 325 }; 326 327 /* vcc8 */ 328 vdd_1v8_lcd_ldo: LDO_REG4 { 329 regulator-name = "vdd_1v8_lcd_ldo"; 330 regulator-always-on; 331 regulator-boot-on; 332 regulator-min-microvolt = <1800000>; 333 regulator-max-microvolt = <1800000>; 334 regulator-state-mem { 335 regulator-on-in-suspend; 336 regulator-suspend-microvolt = <1800000>; 337 }; 338 }; 339 340 /* vcc8 */ 341 vdd_1v0_lcd: LDO_REG6 { 342 regulator-name = "vdd_1v0_lcd"; 343 regulator-always-on; 344 regulator-boot-on; 345 regulator-min-microvolt = <1000000>; 346 regulator-max-microvolt = <1000000>; 347 regulator-state-mem { 348 regulator-on-in-suspend; 349 regulator-suspend-microvolt = <1000000>; 350 }; 351 }; 352 353 /* vcc7 */ 354 vdd_1v8_ldo: LDO_REG7 { 355 regulator-name = "vdd_1v8_ldo"; 356 regulator-always-on; 357 regulator-boot-on; 358 regulator-min-microvolt = <1800000>; 359 regulator-max-microvolt = <1800000>; 360 regulator-state-mem { 361 regulator-off-in-suspend; 362 regulator-suspend-microvolt = <1800000>; 363 }; 364 }; 365 366 /* vcc9 */ 367 vdd_io_sd: LDO_REG9 { 368 regulator-name = "vdd_io_sd"; 369 regulator-always-on; 370 regulator-boot-on; 371 regulator-min-microvolt = <3300000>; 372 regulator-max-microvolt = <3300000>; 373 regulator-state-mem { 374 regulator-on-in-suspend; 375 regulator-suspend-microvolt = <3300000>; 376 }; 377 }; 378 }; 379 }; 380 381 /* M24C32-D */ 382 i2c_eeprom: eeprom@50 { 383 compatible = "atmel,24c32"; 384 reg = <0x50>; 385 pagesize = <32>; 386 }; 387 388 /* M24C32-D Identification page */ 389 i2c_eeprom_id: eeprom@58 { 390 compatible = "atmel,24c32"; 391 reg = <0x58>; 392 pagesize = <32>; 393 }; 394 395 vdd_cpu: regulator@60 { 396 compatible = "fcs,fan53555"; 397 reg = <0x60>; 398 fcs,suspend-voltage-selector = <1>; 399 regulator-always-on; 400 regulator-boot-on; 401 regulator-enable-ramp-delay = <300>; 402 regulator-name = "vdd_cpu"; 403 regulator-min-microvolt = <800000>; 404 regulator-max-microvolt = <1430000>; 405 regulator-ramp-delay = <8000>; 406 vin-supply = <&vdd_sys>; 407 }; 408}; 409 410&pinctrl { 411 pcfg_output_high: pcfg-output-high { 412 output-high; 413 }; 414 415 emmc { 416 /* 417 * We run eMMC at max speed; bump up drive strength. 418 * We also have external pulls, so disable the internal ones. 419 */ 420 emmc_clk: emmc-clk { 421 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>; 422 }; 423 424 emmc_cmd: emmc-cmd { 425 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>; 426 }; 427 428 emmc_bus8: emmc-bus8 { 429 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>, 430 <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 431 <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>, 432 <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>, 433 <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>, 434 <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>, 435 <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>, 436 <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>; 437 }; 438 }; 439 440 gmac { 441 phy_int: phy-int { 442 rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>; 443 }; 444 445 phy_rst: phy-rst { 446 rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; 447 }; 448 }; 449 450 leds { 451 user_led: user-led { 452 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>; 453 }; 454 }; 455 456 pmic { 457 pmic_int: pmic-int { 458 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; 459 }; 460 461 /* Pin for switching state between sleep and non-sleep state */ 462 pmic_sleep: pmic-sleep { 463 rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>; 464 }; 465 }; 466}; 467 468&pwm1 { 469 status = "okay"; 470}; 471 472&saradc { 473 status = "okay"; 474 vref-supply = <&vdd_1v8_ldo>; 475}; 476 477&spi2 { 478 status = "okay"; 479 480 serial_flash: flash@0 { 481 compatible = "micron,n25q128a13", "jedec,spi-nor"; 482 reg = <0x0>; 483 spi-max-frequency = <50000000>; 484 m25p,fast-read; 485 #address-cells = <1>; 486 #size-cells = <1>; 487 status = "okay"; 488 }; 489}; 490 491&tsadc { 492 status = "okay"; 493 rockchip,hw-tshut-mode = <0>; 494 rockchip,hw-tshut-polarity = <0>; 495}; 496 497&vopb { 498 status = "okay"; 499}; 500 501&vopb_mmu { 502 status = "okay"; 503}; 504 505&vopl { 506 status = "okay"; 507}; 508 509&vopl_mmu { 510 status = "okay"; 511}; 512 513&wdt { 514 status = "okay"; 515}; 516