1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Device tree file for Phytec phyCORE-RK3288 SoM 3*4882a593Smuzhiyun * Copyright (C) 2017 PHYTEC Messtechnik GmbH 4*4882a593Smuzhiyun * Author: Wadim Egorov <w.egorov@phytec.de> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 7*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 8*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 9*4882a593Smuzhiyun * whole. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * a) This file is free software; you can redistribute it and/or 12*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 13*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of the 14*4882a593Smuzhiyun * License, or (at your option) any later version. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful, 17*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*4882a593Smuzhiyun * GNU General Public License for more details. 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * Or, alternatively, 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 24*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 25*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 26*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 27*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 28*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 29*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 30*4882a593Smuzhiyun * conditions: 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 33*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun#include <dt-bindings/net/ti-dp83867.h> 46*4882a593Smuzhiyun#include "rk3288.dtsi" 47*4882a593Smuzhiyun#include "rk3288-u-boot.dtsi" 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun/ { 50*4882a593Smuzhiyun model = "Phytec RK3288 phyCORE"; 51*4882a593Smuzhiyun compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * Set the minimum memory size here and 55*4882a593Smuzhiyun * let the bootloader set the real size. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun memory { 58*4882a593Smuzhiyun device_type = "memory"; 59*4882a593Smuzhiyun reg = <0 0x8000000>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun aliases { 63*4882a593Smuzhiyun rtc0 = &i2c_rtc; 64*4882a593Smuzhiyun rtc1 = &rk818; 65*4882a593Smuzhiyun eeprom0 = &i2c_eeprom_id; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun ext_gmac: external-gmac-clock { 69*4882a593Smuzhiyun compatible = "fixed-clock"; 70*4882a593Smuzhiyun #clock-cells = <0>; 71*4882a593Smuzhiyun clock-frequency = <125000000>; 72*4882a593Smuzhiyun clock-output-names = "ext_gmac"; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun io_domains: io_domains { 76*4882a593Smuzhiyun compatible = "rockchip,rk3288-io-voltage-domain"; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun status = "okay"; 79*4882a593Smuzhiyun sdcard-supply = <&vdd_io_sd>; 80*4882a593Smuzhiyun flash0-supply = <&vdd_emmc_io>; 81*4882a593Smuzhiyun flash1-supply = <&vdd_misc_1v8>; 82*4882a593Smuzhiyun gpio1830-supply = <&vdd_3v3_io>; 83*4882a593Smuzhiyun gpio30-supply = <&vdd_3v3_io>; 84*4882a593Smuzhiyun bb-supply = <&vdd_3v3_io>; 85*4882a593Smuzhiyun dvp-supply = <&vdd_3v3_io>; 86*4882a593Smuzhiyun lcdc-supply = <&vdd_3v3_io>; 87*4882a593Smuzhiyun wifi-supply = <&vdd_3v3_io>; 88*4882a593Smuzhiyun audio-supply = <&vdd_3v3_io>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun leds: user-leds { 92*4882a593Smuzhiyun compatible = "gpio-leds"; 93*4882a593Smuzhiyun pinctrl-names = "default"; 94*4882a593Smuzhiyun pinctrl-0 = <&user_led>; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun user { 97*4882a593Smuzhiyun label = "green_led"; 98*4882a593Smuzhiyun gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 99*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 100*4882a593Smuzhiyun default-state = "keep"; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun vdd_emmc_io: vdd-emmc-io { 105*4882a593Smuzhiyun compatible = "regulator-fixed"; 106*4882a593Smuzhiyun regulator-name = "vdd_emmc_io"; 107*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 108*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 109*4882a593Smuzhiyun vin-supply = <&vdd_3v3_io>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun vdd_in_otg_out: vdd-in-otg-out { 113*4882a593Smuzhiyun compatible = "regulator-fixed"; 114*4882a593Smuzhiyun regulator-name = "vdd_in_otg_out"; 115*4882a593Smuzhiyun regulator-always-on; 116*4882a593Smuzhiyun regulator-boot-on; 117*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 118*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun vdd_misc_1v8: vdd-misc-1v8 { 122*4882a593Smuzhiyun compatible = "regulator-fixed"; 123*4882a593Smuzhiyun regulator-name = "vdd_misc_1v8"; 124*4882a593Smuzhiyun regulator-always-on; 125*4882a593Smuzhiyun regulator-boot-on; 126*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 127*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&cpu0 { 132*4882a593Smuzhiyun cpu0-supply = <&vdd_cpu>; 133*4882a593Smuzhiyun operating-points = < 134*4882a593Smuzhiyun /* KHz uV */ 135*4882a593Smuzhiyun 1800000 1400000 136*4882a593Smuzhiyun 1608000 1350000 137*4882a593Smuzhiyun 1512000 1300000 138*4882a593Smuzhiyun 1416000 1200000 139*4882a593Smuzhiyun 1200000 1100000 140*4882a593Smuzhiyun 1008000 1050000 141*4882a593Smuzhiyun 816000 1000000 142*4882a593Smuzhiyun 696000 950000 143*4882a593Smuzhiyun 600000 900000 144*4882a593Smuzhiyun 408000 900000 145*4882a593Smuzhiyun 312000 900000 146*4882a593Smuzhiyun 216000 900000 147*4882a593Smuzhiyun 126000 900000 148*4882a593Smuzhiyun >; 149*4882a593Smuzhiyun}; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun&emmc { 152*4882a593Smuzhiyun status = "okay"; 153*4882a593Smuzhiyun u-boot,dm-pre-reloc; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun bus-width = <8>; 156*4882a593Smuzhiyun cap-mmc-highspeed; 157*4882a593Smuzhiyun disable-wp; 158*4882a593Smuzhiyun non-removable; 159*4882a593Smuzhiyun num-slots = <1>; 160*4882a593Smuzhiyun pinctrl-names = "default"; 161*4882a593Smuzhiyun pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; 162*4882a593Smuzhiyun vmmc-supply = <&vdd_3v3_io>; 163*4882a593Smuzhiyun vqmmc-supply = <&vdd_emmc_io>; 164*4882a593Smuzhiyun}; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun&gmac { 167*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_MAC>; 168*4882a593Smuzhiyun assigned-clock-parents = <&ext_gmac>; 169*4882a593Smuzhiyun clock_in_out = "input"; 170*4882a593Smuzhiyun pinctrl-names = "default"; 171*4882a593Smuzhiyun pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>; 172*4882a593Smuzhiyun phy-handle = <&phy0>; 173*4882a593Smuzhiyun phy-supply = <&vdd_eth_2v5>; 174*4882a593Smuzhiyun phy-mode = "rgmii-id"; 175*4882a593Smuzhiyun snps,reset-active-low; 176*4882a593Smuzhiyun snps,reset-delays-us = <0 10000 1000000>; 177*4882a593Smuzhiyun snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; 178*4882a593Smuzhiyun tx_delay = <0x0>; 179*4882a593Smuzhiyun rx_delay = <0x0>; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun mdio0 { 182*4882a593Smuzhiyun compatible = "snps,dwmac-mdio"; 183*4882a593Smuzhiyun #address-cells = <1>; 184*4882a593Smuzhiyun #size-cells = <0>; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun phy0: ethernet-phy@0 { 187*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 188*4882a593Smuzhiyun reg = <0>; 189*4882a593Smuzhiyun interrupt-parent = <&gpio4>; 190*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 191*4882a593Smuzhiyun ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 192*4882a593Smuzhiyun ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 193*4882a593Smuzhiyun ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 194*4882a593Smuzhiyun enet-phy-lane-no-swap; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun}; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun&hdmi { 200*4882a593Smuzhiyun ddc-i2c-bus = <&i2c5>; 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&i2c0 { 204*4882a593Smuzhiyun status = "okay"; 205*4882a593Smuzhiyun u-boot,dm-pre-reloc; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun clock-frequency = <400000>; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun rk818: pmic@1c { 210*4882a593Smuzhiyun status = "okay"; 211*4882a593Smuzhiyun compatible = "rockchip,rk818"; 212*4882a593Smuzhiyun reg = <0x1c>; 213*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 214*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 215*4882a593Smuzhiyun pinctrl-names = "default"; 216*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 217*4882a593Smuzhiyun rockchip,system-power-controller; 218*4882a593Smuzhiyun wakeup-source; 219*4882a593Smuzhiyun #clock-cells = <1>; 220*4882a593Smuzhiyun u-boot,dm-pre-reloc; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun vcc1-supply = <&vdd_sys>; 223*4882a593Smuzhiyun vcc2-supply = <&vdd_sys>; 224*4882a593Smuzhiyun vcc3-supply = <&vdd_sys>; 225*4882a593Smuzhiyun vcc4-supply = <&vdd_sys>; 226*4882a593Smuzhiyun boost-supply = <&vdd_in_otg_out>; 227*4882a593Smuzhiyun vcc6-supply = <&vdd_sys>; 228*4882a593Smuzhiyun vcc7-supply = <&vdd_misc_1v8>; 229*4882a593Smuzhiyun vcc8-supply = <&vdd_misc_1v8>; 230*4882a593Smuzhiyun vcc9-supply = <&vdd_3v3_io>; 231*4882a593Smuzhiyun vddio-supply = <&vdd_3v3_io>; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun regulators { 234*4882a593Smuzhiyun u-boot,dm-pre-reloc; 235*4882a593Smuzhiyun vdd_log: DCDC_REG1 { 236*4882a593Smuzhiyun regulator-name = "vdd_log"; 237*4882a593Smuzhiyun regulator-always-on; 238*4882a593Smuzhiyun regulator-boot-on; 239*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 240*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 241*4882a593Smuzhiyun regulator-state-mem { 242*4882a593Smuzhiyun regulator-off-in-suspend; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun vdd_gpu: DCDC_REG2 { 247*4882a593Smuzhiyun regulator-name = "vdd_gpu"; 248*4882a593Smuzhiyun regulator-always-on; 249*4882a593Smuzhiyun regulator-boot-on; 250*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 251*4882a593Smuzhiyun regulator-max-microvolt = <1250000>; 252*4882a593Smuzhiyun regulator-state-mem { 253*4882a593Smuzhiyun regulator-on-in-suspend; 254*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 259*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 260*4882a593Smuzhiyun regulator-always-on; 261*4882a593Smuzhiyun regulator-boot-on; 262*4882a593Smuzhiyun regulator-state-mem { 263*4882a593Smuzhiyun regulator-on-in-suspend; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun vdd_3v3_io: DCDC_REG4 { 268*4882a593Smuzhiyun regulator-name = "vdd_3v3_io"; 269*4882a593Smuzhiyun regulator-always-on; 270*4882a593Smuzhiyun regulator-boot-on; 271*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 272*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 273*4882a593Smuzhiyun regulator-state-mem { 274*4882a593Smuzhiyun regulator-on-in-suspend; 275*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun vdd_sys: DCDC_BOOST { 280*4882a593Smuzhiyun regulator-name = "vdd_sys"; 281*4882a593Smuzhiyun regulator-always-on; 282*4882a593Smuzhiyun regulator-boot-on; 283*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 284*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 285*4882a593Smuzhiyun regulator-state-mem { 286*4882a593Smuzhiyun regulator-on-in-suspend; 287*4882a593Smuzhiyun regulator-suspend-microvolt = <5000000>; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun /* vcc9 */ 292*4882a593Smuzhiyun vdd_sd: SWITCH_REG { 293*4882a593Smuzhiyun regulator-name = "vdd_sd"; 294*4882a593Smuzhiyun regulator-always-on; 295*4882a593Smuzhiyun regulator-boot-on; 296*4882a593Smuzhiyun regulator-state-mem { 297*4882a593Smuzhiyun regulator-off-in-suspend; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun /* vcc6 */ 302*4882a593Smuzhiyun vdd_eth_2v5: LDO_REG2 { 303*4882a593Smuzhiyun regulator-name = "vdd_eth_2v5"; 304*4882a593Smuzhiyun regulator-always-on; 305*4882a593Smuzhiyun regulator-boot-on; 306*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 307*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 308*4882a593Smuzhiyun regulator-state-mem { 309*4882a593Smuzhiyun regulator-on-in-suspend; 310*4882a593Smuzhiyun regulator-suspend-microvolt = <2500000>; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* vcc7 */ 315*4882a593Smuzhiyun vdd_1v0: LDO_REG3 { 316*4882a593Smuzhiyun regulator-name = "vdd_1v0"; 317*4882a593Smuzhiyun regulator-always-on; 318*4882a593Smuzhiyun regulator-boot-on; 319*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 320*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 321*4882a593Smuzhiyun regulator-state-mem { 322*4882a593Smuzhiyun regulator-on-in-suspend; 323*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun /* vcc8 */ 328*4882a593Smuzhiyun vdd_1v8_lcd_ldo: LDO_REG4 { 329*4882a593Smuzhiyun regulator-name = "vdd_1v8_lcd_ldo"; 330*4882a593Smuzhiyun regulator-always-on; 331*4882a593Smuzhiyun regulator-boot-on; 332*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 333*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 334*4882a593Smuzhiyun regulator-state-mem { 335*4882a593Smuzhiyun regulator-on-in-suspend; 336*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* vcc8 */ 341*4882a593Smuzhiyun vdd_1v0_lcd: LDO_REG6 { 342*4882a593Smuzhiyun regulator-name = "vdd_1v0_lcd"; 343*4882a593Smuzhiyun regulator-always-on; 344*4882a593Smuzhiyun regulator-boot-on; 345*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 346*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 347*4882a593Smuzhiyun regulator-state-mem { 348*4882a593Smuzhiyun regulator-on-in-suspend; 349*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun /* vcc7 */ 354*4882a593Smuzhiyun vdd_1v8_ldo: LDO_REG7 { 355*4882a593Smuzhiyun regulator-name = "vdd_1v8_ldo"; 356*4882a593Smuzhiyun regulator-always-on; 357*4882a593Smuzhiyun regulator-boot-on; 358*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 359*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 360*4882a593Smuzhiyun regulator-state-mem { 361*4882a593Smuzhiyun regulator-off-in-suspend; 362*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun /* vcc9 */ 367*4882a593Smuzhiyun vdd_io_sd: LDO_REG9 { 368*4882a593Smuzhiyun regulator-name = "vdd_io_sd"; 369*4882a593Smuzhiyun regulator-always-on; 370*4882a593Smuzhiyun regulator-boot-on; 371*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 372*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 373*4882a593Smuzhiyun regulator-state-mem { 374*4882a593Smuzhiyun regulator-on-in-suspend; 375*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun }; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun /* M24C32-D */ 382*4882a593Smuzhiyun i2c_eeprom: eeprom@50 { 383*4882a593Smuzhiyun compatible = "atmel,24c32"; 384*4882a593Smuzhiyun reg = <0x50>; 385*4882a593Smuzhiyun pagesize = <32>; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun /* M24C32-D Identification page */ 389*4882a593Smuzhiyun i2c_eeprom_id: eeprom@58 { 390*4882a593Smuzhiyun compatible = "atmel,24c32"; 391*4882a593Smuzhiyun reg = <0x58>; 392*4882a593Smuzhiyun pagesize = <32>; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun vdd_cpu: regulator@60 { 396*4882a593Smuzhiyun compatible = "fcs,fan53555"; 397*4882a593Smuzhiyun reg = <0x60>; 398*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 399*4882a593Smuzhiyun regulator-always-on; 400*4882a593Smuzhiyun regulator-boot-on; 401*4882a593Smuzhiyun regulator-enable-ramp-delay = <300>; 402*4882a593Smuzhiyun regulator-name = "vdd_cpu"; 403*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 404*4882a593Smuzhiyun regulator-max-microvolt = <1430000>; 405*4882a593Smuzhiyun regulator-ramp-delay = <8000>; 406*4882a593Smuzhiyun vin-supply = <&vdd_sys>; 407*4882a593Smuzhiyun }; 408*4882a593Smuzhiyun}; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun&pinctrl { 411*4882a593Smuzhiyun pcfg_output_high: pcfg-output-high { 412*4882a593Smuzhiyun output-high; 413*4882a593Smuzhiyun }; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun emmc { 416*4882a593Smuzhiyun /* 417*4882a593Smuzhiyun * We run eMMC at max speed; bump up drive strength. 418*4882a593Smuzhiyun * We also have external pulls, so disable the internal ones. 419*4882a593Smuzhiyun */ 420*4882a593Smuzhiyun emmc_clk: emmc-clk { 421*4882a593Smuzhiyun rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>; 422*4882a593Smuzhiyun }; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun emmc_cmd: emmc-cmd { 425*4882a593Smuzhiyun rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun emmc_bus8: emmc-bus8 { 429*4882a593Smuzhiyun rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>, 430*4882a593Smuzhiyun <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 431*4882a593Smuzhiyun <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>, 432*4882a593Smuzhiyun <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>, 433*4882a593Smuzhiyun <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>, 434*4882a593Smuzhiyun <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>, 435*4882a593Smuzhiyun <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>, 436*4882a593Smuzhiyun <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun gmac { 441*4882a593Smuzhiyun phy_int: phy-int { 442*4882a593Smuzhiyun rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>; 443*4882a593Smuzhiyun }; 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun phy_rst: phy-rst { 446*4882a593Smuzhiyun rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun }; 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun leds { 451*4882a593Smuzhiyun user_led: user-led { 452*4882a593Smuzhiyun rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>; 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun }; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun pmic { 457*4882a593Smuzhiyun pmic_int: pmic-int { 458*4882a593Smuzhiyun rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun /* Pin for switching state between sleep and non-sleep state */ 462*4882a593Smuzhiyun pmic_sleep: pmic-sleep { 463*4882a593Smuzhiyun rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>; 464*4882a593Smuzhiyun }; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun}; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun&pwm1 { 469*4882a593Smuzhiyun status = "okay"; 470*4882a593Smuzhiyun}; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun&saradc { 473*4882a593Smuzhiyun status = "okay"; 474*4882a593Smuzhiyun vref-supply = <&vdd_1v8_ldo>; 475*4882a593Smuzhiyun}; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun&spi2 { 478*4882a593Smuzhiyun status = "okay"; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun serial_flash: flash@0 { 481*4882a593Smuzhiyun compatible = "micron,n25q128a13", "jedec,spi-nor"; 482*4882a593Smuzhiyun reg = <0x0>; 483*4882a593Smuzhiyun spi-max-frequency = <50000000>; 484*4882a593Smuzhiyun m25p,fast-read; 485*4882a593Smuzhiyun #address-cells = <1>; 486*4882a593Smuzhiyun #size-cells = <1>; 487*4882a593Smuzhiyun status = "okay"; 488*4882a593Smuzhiyun }; 489*4882a593Smuzhiyun}; 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun&tsadc { 492*4882a593Smuzhiyun status = "okay"; 493*4882a593Smuzhiyun rockchip,hw-tshut-mode = <0>; 494*4882a593Smuzhiyun rockchip,hw-tshut-polarity = <0>; 495*4882a593Smuzhiyun}; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun&vopb { 498*4882a593Smuzhiyun status = "okay"; 499*4882a593Smuzhiyun}; 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun&vopb_mmu { 502*4882a593Smuzhiyun status = "okay"; 503*4882a593Smuzhiyun}; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun&vopl { 506*4882a593Smuzhiyun status = "okay"; 507*4882a593Smuzhiyun}; 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun&vopl_mmu { 510*4882a593Smuzhiyun status = "okay"; 511*4882a593Smuzhiyun}; 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun&wdt { 514*4882a593Smuzhiyun status = "okay"; 515*4882a593Smuzhiyun}; 516